• Title/Summary/Keyword: multipath execution

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Fixed point DSP Implementation of the IEEE 802.11a WLAN modem synchronizer (IEEE 802.11a 무선랜 모뎀 동기부의 고정 소수점 DSP 구현)

  • 정중현;이서구;정윤호;김재석;서정욱;최종찬
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.517-520
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    • 2003
  • Orthogonal Frequency Division Multiplexing (OFDM) is a promising technology for high speed multimedia communication in a frequency selective multipath channel. In this paper, Software IPs for the synchronizer of IEEE 802.11a Wireless LAN system are designed and optimized for TI's TMS320C6201 fixed point DSP. As a result of the execution cycles of the target DSP for each functions of the system, an efficient HW/SW partitioning method can be considered.

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Performance Improvement of Single Chip Multiprocessor using Concurrent Branch Execution (분기 동시 수행을 이용한 단일 칩 멀티프로세서의 성능 개선)

  • Lee, Seung-Ryul;Kim, Jun-Shik;Choi, Jae-Hyeok;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.61-71
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    • 2007
  • The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.