• Title/Summary/Keyword: multi-core processing

Search Result 218, Processing Time 0.028 seconds

The Pixel Shading on Multi Core GP-GPU with Dual Phase Architecture (듀얼 페이즈 구조의 멀티 코어 GP-GPU를 이용한 픽셀 셰이딩)

  • Kim, Jun-Seo;Park, Tae-Ryong;Lee, Kwang-Yeob
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2010.10a
    • /
    • pp.339-342
    • /
    • 2010
  • 최근 프로세서가 클럭 향상의 한계에 부딪힘에 따라, 프로세서의 성능을 향상시키기 위해 멀티 코어 기반의 병렬처리를 이용한 방법들이 제안 되고 있다. 본 논문은 여러개의 연산기를 한 명령어 사이클에 동시에 사용할 수 있는 MIMD(Multiple Instruction, Multiple Data) 구조를 가지며, Scratch Counter를 이용해 멀티 코어와 멀티 스레드의 작업을 할당하는 구조의 GP-GPU(General Purpose - Graphics Processing Unit)를 활용해 멀티 코어, 멀티 스레드 환경에서의 효율적인 픽셀 셰이딩 방법을 설계 하였다. 선형 안개 픽셀 셰이딩의 경우 싱글코어에서 18.3 FPS이며 4개의 멀티코어 GP-GPU에서는 4배가 증가한 73.2 FPS 결과를 얻었다.

  • PDF

8K Programmable Multimedia Platform based on SRP (SRP 를 기반으로 하는 8K 프로그래머블 멀티미디어 플랫폼)

  • Lee, Wonchang;Kim, Minsoo;Song, Joonho;Kim, Jeahyun;Lee, Shihwa
    • Proceedings of the Korean Society of Broadcast Engineers Conference
    • /
    • 2014.06a
    • /
    • pp.163-165
    • /
    • 2014
  • In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

  • PDF

Differentiated Services Based Admission Control and Multi Path Routing Algorithm for IPv6

  • Farooq, Muhammad Omer;Aziz, Sadia
    • Journal of Information Processing Systems
    • /
    • v.5 no.2
    • /
    • pp.97-104
    • /
    • 2009
  • In this paper we propose a Differentiated Services Based Admission Control and Routing Algorithm for IPv6 (ACMRA). The basic DiffServ architecture lacks an admission control mechanism, the injection of more QoS sensitive traffic into the network can cause congestion at the core of the network. Our Differentiated Services Based Admission Control and Routing Algorithm for IPv6 combines the admission control phase with the route finding phase, and our routing protocol has been designed in a way to work alongside DiffServ based networks. The Differentiated Services Based Admission Control and Routing Algorithm for IPv6 constructs label switched paths in order to provide rigorous QoS provisioning. We have conducted extensive simulations to validate the effectiveness and efficiency of our proposed admission control and routing algorithm. Simulation Results show that the Differentiated Services Based Admission Control and Routing Algorithm for IPv6 provides an excellent packet delivery ratio, reduces the control packets' overhead, and makes use of the resources present on multiple paths to the destination network, while almost each admitted flow shows compliance with its Service Level Agreement.

The effect of mechanical working on processing the Bi-2223/Ag tapes using PIT method

  • Oh, S.S.;Ha, D.W.;Kim, S.C.;Bae, S.W.;Kwon, Y.K.;Ryu, K.S.;Ha, H.S.
    • 한국초전도학회:학술대회논문집
    • /
    • v.10
    • /
    • pp.276-279
    • /
    • 2000
  • When high temperature superconducting tapes is fabricated using the PIT (Powder In Tube) method, the length of HTS tapes is increased more than 500 ${\sim}$ 1,000 times of initial powder packed billet. On mechanical processing, heterogeneous properties between the ceramic superconducting core and Ag/Ag alloy sheath occur the non-uniformity deformation as like sausaging that deteriorate the critical current properties of HTS tapes. In this study, we investigated the workability of Bi-2223/Ag/Ag alloy sheath tapes fabricated by the PIT method involving a number of different mechanical processes, multi drawing and rolling. In order to obtain the high critical current density and high uniformity of Bi-2223/Ag sheath tapes, the influences of powder packing density, drawing die angle and rolling parameters were studied. We found that the roll diameter is an important variable in the rolling process, as critical current of tapes rolled using 250 mm rolls was higher than that using 150 mm rolls.

  • PDF

Exploiting Back-end Fusion in Multi-Core Processors (다중 코어 환경에서의 Back-end Fusion 구현)

  • Park, Jong Hyun;Jeong, I Poom;Ro, Won Woo
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2014.04a
    • /
    • pp.33-36
    • /
    • 2014
  • 최근 스마트폰이나 태블릿 PC 등의 모바일 디바이스가 상용화 되어감에 따라 그 안에서 핵심적인 처리기능을 담당하는 프로세서의 코어 수가 점차적으로 늘어나고 있다. 많은 수의 코어를 효율적으로 사용하기 위해 여러 가지 메커니즘이 구현되어 있으나, 단일 프로세스를 순차적으로 실행하는 경우 여전히 성능에서의 한계가 존재한다. 병렬화 되어 있지 않은 프로세스의 경우, Amdahl's Law[1]에 따르면 순차적으로 실행을 할 수 밖에 없는 부분이 존재하고, 이 부분은 하나의 코어에서만 실행되기 때문에 많은 연산 자원들이 낭비되는 현상이 발생한다. 본 논문은 다중 코어 환경에서 이러한 잉여자원을 효과적으로 사용하기 위해 Back-end Fusion 이라는 구조를 제안하여 프로세서의 성능 향상을 위한 연구를 진행하였다. Back-end Fusion 이란, 연산 처리를 담당하는 back-end 부분(execution unit, writeback 단계 등)을 필요에 따라 코어 간에 동적으로 재구성하여 성능을 향상시키는 메커니즘이다. 이 재구성된 프로세서의 back-end 를 효율적으로 사용하기 위해, 종속성과 로드 밸런스 등을 고려한 인스트럭션 분배 알고리즘을 함께 제안한다. Intel 사의 x86 Instruction Set Architecture(ISA)를 기반으로 한 시뮬레이터를 이용하여 Back-end Fusion 프로세서의 성능을 측정 해 본 결과 기존의 단일 코어 프로세서에 비해 평균 32.2%의 성능 향상을 확인할 수 있었다.

3D Segmentation for High-Resolution Image Datasets Using a Commercial Editing Tool in the IoT Environment

  • Kwon, Koojoo;Shin, Byeong-Seok
    • Journal of Information Processing Systems
    • /
    • v.13 no.5
    • /
    • pp.1126-1134
    • /
    • 2017
  • A variety of medical service applications in the field of the Internet of Things (IoT) are being studied. Segmentation is important to identify meaningful regions in images and is also required in 3D images. Previous methods have been based on gray value and shape. The Visible Korean dataset consists of serially sectioned high-resolution color images. Unlike computed tomography or magnetic resonance images, automatic segmentation of color images is difficult because detecting an object's boundaries in colored images is very difficult compared to grayscale images. Therefore, skilled anatomists usually segment color images manually or semi-automatically. We present an out-of-core 3D segmentation method for large-scale image datasets. Our method can segment significant regions in the coronal and sagittal planes, as well as the axial plane, to produce a 3D image. Our system verifies the result interactively with a multi-planar reconstruction view and a 3D view. Our system can be used to train unskilled anatomists and medical students. It is also possible for a skilled anatomist to segment an image remotely since it is difficult to transfer such large amounts of data.

A Tool for Visualizing Task Scheduling of Multi-Core Embedded Systems (멀티코어 임베디드 시스템 스케줄링 결과 시각화 도구)

  • Ma, Yuseung;Woo, Duk-Kyun;Kim, Sang Cheol;Song, Junkeun;Lee, Jung-Woo;Mah, Pyeongsoo;Kim, Seon-Tae
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2015.10a
    • /
    • pp.208-210
    • /
    • 2015
  • 임베디드 시스템에서 멀티코어 프로세스의 채택이 늘어나고 있다. 멀티코어 시스템이 태스크들을 효율적으로 병렬화하여 성능을 극대화하였는지 살펴보기 위해서는 태스크들의 스케줄링 결과를 분석하고 시각화 해주는 도구가 필요하다. 본 논문에서는 멀티코어 임베디드 시스템을 위한 태스크 스케줄링 결과 시각화 도구를 소개한다. 자원 제약이 있는 임베디드 타켓 디바이스의 부하를 줄이기 위해 스케줄링 결과는 호스트 컴퓨터에 전달되어 분석 및 시각화된다. 시각화 형태는 시스템의 전체 동작을 한 눈에 파악할 수 있게 해주는 그래프 형태와 정밀한 분석을 가능하게 해 주는 리스트 형태로 제공된다. 제시된 도구는 멀티코어 임베디드 시스템의 태스크들의 스케줄링 결과를 쉽고 정확하게 파악할 수 있게 해 주어 시스템의 성능 향상에 도움을 준다.

Machine Learning Data Analysis for Tool Wear Prediction in Core Multi Process Machining (코어 다중가공에서 공구마모 예측을 위한 기계학습 데이터 분석)

  • Choi, Sujin;Lee, Dongju;Hwang, Seungkuk
    • Journal of the Korean Society of Manufacturing Process Engineers
    • /
    • v.20 no.9
    • /
    • pp.90-96
    • /
    • 2021
  • As real-time data of factories can be collected using various sensors, the adaptation of intelligent unmanned processing systems is spreading via the establishment of smart factories. In intelligent unmanned processing systems, data are collected in real time using sensors. The equipment is controlled by predicting future situations using the collected data. Particularly, a technology for the prediction of tool wear and for determining the exact timing of tool replacement is needed to prevent defected or unprocessed products due to tool breakage or tool wear. Directly measuring the tool wear in real time is difficult during the cutting process in milling. Therefore, tool wear should be predicted indirectly by analyzing the cutting load of the main spindle, current, vibration, noise, etc. In this study, data from the current and acceleration sensors; displacement data along the X, Y, and Z axes; tool wear value, and shape change data observed using Newroview were collected from the high-speed, two-edge, flat-end mill machining process of SKD11 steel. The support vector machine technique (machine learning technique) was applied to predict the amount of tool wear using the aforementioned data. Additionally, the prediction accuracies of all kernels were compared.

Defect detection of vacuum insulation panel using image analysis based on corner feature detection (코너 특정점 기반의 영상분석을 활용한 진공단열재 결함 검출)

  • Kim, Beom-Soo;Yang, Jeonghyeon;Kim, Yeonwon
    • Journal of the Korean institute of surface engineering
    • /
    • v.55 no.6
    • /
    • pp.398-402
    • /
    • 2022
  • Vacuum Insulation Panel (VIP) is an high energy efficient insulation system that facilitate slim but high insulation performance, based on based on a porous core material evacuated and encapsulated in a multi-barrier envelope. Although VIP has been on the market for decades now, it wasn't until recently that efforts have been initiated to propose a standard on aging testing. One of the issues regarding VIP is its durability and aging due to pressure and moisture dependent increase of the initial low thermal conductivity with time. It is hard to visually determine at an early stage. Recently, a method of analyzing the damage on the a material surface by applying image processing technology has been widely used. These techniques provide fast and accurate data with a non-destructive way. In this study, the surface VIP images were analyzed using the Harris corner detection algorithm. As a result, 171,333 corner points in the normal packaging were detected, whereas 32,895 of the defective packaging, which were less than the normal packaging. were detected. These results are considered to provide meaningful information for the determination of VIP condition.

Circuit Design Method to Solve the Processing Error and the Processing Speed Decreasing Problems in Multi-core Hardware In-the-Loop Simulation (Hardware In-the-Loop Simulation의 다중 코어 연산시 발생할 수 있는 연산 오류 및 연산속도 저하를 해결하기 위한 회로 구성 기법 제안)

  • CHAE, BEOM-SEOK;JEON, JAE-HYUN;KIM, KYUNG-SUE;OH, HYUN-SEOK;PARK, CHEOL-HYUN;LEE, JEONG-JOON
    • Proceedings of the KIPE Conference
    • /
    • 2020.08a
    • /
    • pp.421-422
    • /
    • 2020
  • Hardware In-the-Loop simulation(HIL)은 실제 하드웨어 시스템을 실시간 모사할 수 있는 시뮬레이션 장비로 연구 및 개발 기간의 단축, 비용저감 등의 장점을 앞세워 다양한 전력전자 분야에 사용되고 있다. 실제 하드웨어를 그대로 모사하는 것이 HIL의 목적이기 때문에 HIL 장비는 검증의 실시간성과 출력된 결과의 정확성이 무엇보다도 중요하다고 할 수 있다. 하지만 코어간의 데이터를 주고받는 과정에서 HIL의 연산 속도 및 정확성을 저해하는 요인들이 발생하게 된다. 본 연구에서는 HIL 장비를 이용해 복잡한 시스템을 구현함에 있어서 연산속도 및 정확성을 저해하는 요인들을 찾아내고 이를 해결하기 위한 방법을 제안한다. 제안된 연산속도 개선 및 정확성 개선 방법의 타당성은 프로세서의 연산 속도 변화량, HIL 및 시험 결과 파형의 비교 분석을 통해 검증되었다.

  • PDF