• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.9-9
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• 2010

In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.324-330
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• 2004

In this paper, we propose the TCM(Trellis coded modulation) decoding scheme that reduces the number of operations in branch metric with STBC(space time block codes) channel information and present the implementation results. The proposed TCM decoding scheme needs only 1 signal point in each TCM subset. Using bias point scheme, It detects the minimum distance symbol. The proposed TCM decoding scheme can reduce the branch metric calculations. In case of 16QAM 8 subset, the reduction ratio is about 50％ and for 64QAM 8 subset, about 80％ reduction can be obtained. The results of logic synthesis for the TCM and STBC decoder with the proposed scheme are 57.6K gate count.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.7
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• pp.1044-1052
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• 1999

A 2-stage 1 watt MMIC(Monolithic Microwave Integrated Circuits) HPA(High Power Amplifiers) at 20 GHz band has been designed and fabricated. The $0.15\mu\textrm{m}$ with the width of $400\mu\textrm{m}$for single device pHEMT technology was used for the fabrication of this MMIC HPA. Due to the series feedback technique from source to ground, bias circuits and stabilization circuits on the main microstrip line, the stability factors(Ks) are more than one at full frequency. The independent operation for each stage and excellent S11, S22 less than -20 dB have been obtained by using lange couplers. For beginning the easy design, linear S-parameters have been extracted from the nonlinear equivalent circuit in foundry library, and equivalent circuits of devices at in/output ports were calculated from this S-parameters. The measured performances, which are in well agreement with the predicted ones, showed the MMIC HPA in this paper has the minimum 15 dB of linear gain, -20 dB of reflection coefficients and 31 dBm of output power over 17~25 GHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.619-628
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• 2019

In this paper, we designed a beta ray sensor for a true random number generator. Instead of biasing the gate of the PMOS feedback transistor to a DC voltage, the current flowing through the PMOS feedback transistor is mirrored through a current bias circuit designed to be insensitive to PVT fluctuations, thereby minimizing fluctuations in the signal voltage of the CSA. In addition, by using the constant current supplied by the BGR (Bandgap Reference) circuit, the signal voltage is charged to the VCOM voltage level, thereby reducing the change in charge time to enable high-speed sensing. The beta ray sensor designed with 0.18㎛ CMOS process shows that the minimum signal voltage and maximum signal voltage of the CSA circuit which are resulted from corner simulation are 205mV and 303mV, respectively. and the minimum and maximum widths of the pulses generated by comparing the output signal through the pulse shaper with the threshold voltage (VTHR) voltage of the comparator, were 0.592㎲ and 1.247㎲, respectively. resulting in high-speed detection of 100kHz. Thus, it is designed to count up to 100 kilo pulses per second.

• Korean Journal of Environmental Biology
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• v.39 no.4
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• pp.526-535
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• 2021

Spatial sampling design plays an important role in GIS-based modeling studies because it increases modeling efficiency while reducing the cost of sampling. In the field of agricultural systems, research demand for high-resolution spatial databased modeling to predict and evaluate climate change impacts is growing rapidly. Accordingly, the need and importance of spatial sampling design are increasing. The purpose of this study was to design spatial sampling of paddy fields (11,386 grids with 1 km spatial resolution) in Korea for use in agricultural spatial modeling. A stratified random sampling design was developed and applied in 2030s, 2050s, and 2080s under two RCP scenarios of 4.5 and 8.5. Twenty-five weather and four soil characteristics were used as stratification variables. Stratification and sample allocation were optimized to ensure minimum sample size under given precision constraints for 16 target variables such as crop yield, greenhouse gas emission, and pest distribution. Precision and accuracy of the sampling were evaluated through sampling simulations based on coefficient of variation (CV) and relative bias, respectively. As a result, the paddy field could be optimized in the range of 5 to 21 strata and 46 to 69 samples. Evaluation results showed that target variables were within precision constraints (CV<0.05 except for crop yield) with low bias values (below 3%). These results can contribute to reducing sampling cost and computation time while having high predictive power. It is expected to be widely used as a representative sample grid in various agriculture spatial modeling studies.