• Journal of Korean Society of Transportation
• /
• v.33 no.1
• /
• pp.70-80
• /
• 2015

In recent years, tram has been the focus of a new mode of public transportation that can solve traffic jams and decrease public transit usage and environmental problem. This research is in the works to develop a tram signal controller and signal control strategies, and aim to resolve the problem of what could happen if a tram system was installed in general road. We developed the hierarchical signal control strategies to obtain a minimum tram bandwidth and to minimize vehicle delay, in order to perform a priority control to include passive and active signal priority control strategies. The strategies was produced for S/W and H/W, it is based in standard traffic signal controller. We conducted a micro simulation test to evaluate the hierarchical signal control strategies, which showed that the developed optimization model is effective to prevent a tram's stop in intersection, to reduce a tram's travel time and vehicle's delay.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.1
• /
• pp.9-21
• /
• 2016

Nowadays various methods for energy saving have been studied in IP networks. This paper suggests a 2-phase OSPF routing method for energy saving on IP networks having various energy profiles and analyzes its characteristics. The phase-1 of the routing is an OSPF routing method considering the energy cost of devices besides existing metrics to minimize energy consumption. In the phase-2 of the routing, it makes core nodes go into sleep sate for energy saving and reroutes the paths affected by sleeping core nodes. At this time, we confirm that the characteristics of mean delay and energy efficiency can be satisfied by limiting an allowable hop number in the reroute paths, and utilization rate of nodes and links for assuring energy saving and network-level QoS. Since the efficiency of energy saving and delay characteristics differ according to selection methods of core nodes to go into sleep state, it is that the a method of core node selection based on MP(minimum_path) is more excellent than others in terms of network-level QoS and energy saving in IP networks.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.16 no.6
• /
• pp.53-66
• /
• 2017

In order to improve traffic flow and vehicular safety, installation of roundabouts is encouraging recently. Roundabouts are generally installed at which traffic flow and pedestrian flow is relatively low intersections. Roundabouts reduce vehicle speed, minimize vehicle weaving, and reduce critical conflict points. For these reasons, roundabouts are generally operated unprotected pedestrian crosswalk, thus a shortcoming for pedestrian safety always exists at roundabouts. The purpose of this study is developing a dynamic signal metering algorithm for traffic and pedestrian at four-way-approach with two-lane roundabouts in which three different operation algorithms(fixed-time pedestrian, vehicle signal metering, and vehicle and pedestrian signal metering) are suggested and its performance is tested by using VISSIM. The results of the fixed pedestrian signal operation show that there is a big average delay increase in general and that increases up to 51.4 seconds/vehicle(42.5%) when the total number of approaching vehicle is 3,800 vehicle/hour. However, the results of the simultaneous dynamic signal metering operation for the vehicle and pedestrian crossing with push button show that there is a substantial average delay reduction up to 40.6 seconds/vehicle(42.7%) when the total number of approaching vehicle is 3,000 vehicle/hour.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.10 no.2
• /
• pp.22-34
• /
• 2011

This paper presents the investigation results of a research on how engineers can analyze the economic effect of the ETCS(Electronic Toll Collection System) installed to minimize the vehicle delays on freeway tollgates during toll payments. This research considered this economic effect to occur in the form of vehicle passing time reductions at the ETCS, and the multi-service queuing theory was applied to estimate these values. This research found: 1) When vehicles approaching tollgates show Poisson distribution and the service time of the ETCS shows Exponential distribution, the multi-service queuing theory would be applicable for estimating vehicle passing times at toll-gates, 2) Despite the ETCS placement, exit sections of tollgates give a greater reduction of vehicle passing times than entering sections due to more delays at conventional toll payments, and 3)The ETCS would not guarantee vehicle passing time reductions all the time, because in such a case as many vehicles were queuing at the ETCS, the total delay level for a toll gate would increase greatly. In addition, in order to examine the accuracy of the estimated vehicle passing values, this research compared the values from the multi-service queuing theory with the observed values from a set of field survey values at freeway toll-gates, and found that the two values were in a good agreement with a very low error range of 1-3 seconds per vehicle. Based on this result, the multi-service queuing theory was recommended for practice.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.10B
• /
• pp.939-945
• /
• 2008

Tn this paper we described the process and the results of an implementation of Internet terminal using G.729.1 wideband speech codec for next generation network. For this purpose firstly we chose a high performance RISC application processor having DSP features for speech codec processing and enhanced Multimedia Accelerator(eMMA) function for video codec. In the implementation of this terminal, we used G.729.1 codec recently standardized in ITU-T which is a new scalable speech and audio codec that extends 0.729 speech coding standard. To adopt G.729.1 codec to this terminal we transformed most of the fixed point C codes which require more complexity into assembly codes so as to minimize processing time in the processor. As a result of this work we reduced the execution time of the original C codes about 80% and operated in real time on the terminal. For video we used H.263/MPEG-4 codec which is supported by the eMMA with hardware in the processor. In the SIP call processing test connected to real network we obtained under looms end-to-end delay and 3.8 MOS value measured with PESQ instrument. Besides this terminal operated well with commercial terminals.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.10
• /
• pp.17-28
• /
• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The KIPS Transactions:PartA
• /
• v.11A no.2
• /
• pp.195-202
• /
• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.63-73
• /
• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Korean Association of Oral and Maxillofacial Surgeons
• /
• v.25 no.4
• /
• pp.356-360
• /
• 1999

PURPOSE : This is to review the complicated jaw fractures that had been referred for revision of the unsatisfactory results, and to provide proper managements for the easily complicated jaw fractures. MATERIALS & METHODS : Twenty-nine patients who had been revised due to malunion or complicated fractures of facial bones for last 3 years were reviewed. The main problems required for revision, type of fractures complicated, the primary managements to be reclaimed, the specialties to be involved, the management to be reclaimed, time elapsed to seek reoperation, type of revision surgeries, residual complication were analysed with medical records, radiographs and final examinations. RESULTS: The major complaints were malocclusion(79.3%), facial disfigurement(41.3%), TMJ problems (13.7%), neurologic problems(10.3%), non-union(10.3%), and infection(6.8%). Unsatisfactory results were occurred most frequently after improper management of the multiple fractures of the mandible (62.2%), combined fractures of maxilla and mandible (20.6%), fracture of zygomatico-maxillary complex and midpalate (17.2%). The complications to be corrected were widened or collapsed dental arches (79.3%), improperly reduced condyles (41.3%), painful TMJ (34.4%), limited jaw excursion (31.0%), over-reduction of zygoma (13.7%), and nonunion with infection(13.7%). and dysesthesia (10.3%). The primary managements were nendereet by plastic surgeons in 82.7%(24/29) and by oral surgeons in 7.6%(2/29). Main causes of malunion are inadequate ORIF in 76%, unawareness & delay in 17%, and delayed due to systemic cares in 17%. 76% of 29 patients had been in state of intermaxillary fixation for over 4 weeks. Revision were done by means of "refracture and ORIF"in 48.2%(14/29), orthognathic osteotomies with bone grafts in 55.1%(16/29), and camouflage countering & alloplastic implantations in 37.9%(11/29), TMJ surgeries in 17.2%, micro-neurosurgeries in 11.6%. Residual complications were limited mouth opening in 24.1% (7/29), paresthesia in 13.7%, resorption of reduced condyle in 10.3%. CONCLUSIONS : Failure of initial treatment of jaw fractures is due to improper diagnosis and inadequate treatment with lack of sufficient knowledge of stomatognathic system. It is crucial to judge jaw fracture and patients accurately, moreover, the best way of treatments has to be selected. Consideration of these factors in treatment could minimize the complication of jaw fractures.

• The KIPS Transactions:PartD
• /
• v.10D no.4
• /
• pp.591-602
• /
• 2003

Delay and discontinuance phenomenon of service are cause by sudden increase of the network communication amount and the quantity consumed of resources when Internet users are driven excessively to a conventional single large database sewer. To solve these problems, spatial database cluster consisted of several single nodes on high-speed network to offer high-performance is risen. But, research about spatial join operation that can reduce the performance of whole system in case process at single node is not achieved. So, in this paper, we propose efficient parallel spatial join processing method in a spatial database cluster system that uses data partitions and replications method that considers the characteristics of space data. Since proposed method does not need the creation step and the assignment step of tasks, and does not occur additional message transmission between cluster nodes that appear in existent parallel spatial join method, it shows performance improvement of 23% than the conventional parallel R-tree spatial join for a shared-nothing architecture about expensive spatial join queries. Also, It can minimize the response time to user because it removes redundant refinement operation at each cluster node.