• Title/Summary/Keyword: metal/insulator/metal structure

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Preparation of the SBT Film on the LZO/Si Structure for FRAM Application

  • Im, Jong-Hyun;Jeon, Ho-Seung;Kim, Joo-Nam;Park, Byung-Eun;Kim, Chul-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.140-141
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    • 2007
  • To fabricate the metal-ferroelectric-insulator-semiconductor (MFIS) structure for the ferroelectric random access memory (FRAM) application, we prepared the ferroelectric $Sr_{0.9}Bi_{2.1}Ta_2O_9$ (SBT) and the insulator LaZrOx (LZO) thin films on the silicon substrate using a sol-gel method. In this study, we will investigate the feasibility of the SBT/LZO/Si structure as one of the promising gate configuration for the 1-transistor (1-T) type FRAM, by measurements of the electrical properties and the physical properties.

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MISFET type H2 sensor using pd-black catalytic metal gate for high performance (Pd-black 촉매금속 이용한 고성능 MISFET 형 수소센서)

  • Kang, Ki-Ho;Cho, Yong-Soo;Han, Sang-Do;Choi, Sie-Young
    • Journal of Sensor Science and Technology
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    • v.15 no.2
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    • pp.90-96
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    • 2006
  • We have fabricated the Pd-blck/NiCr gate MISFET-type $H_2$ sensor to detect the hydrogen in atmosphere. A differential pair-type structure was used to minimize the intrinsic voltage drift of the MISFET. The Pd-black film was deposited in the argon environment by thermal evaporation. In order to eliminate the blister formation in the surface of the hydrogen sensing gate metal, Pd-black/NiCr double metal layer was deposited on the gate insulator. The scanning electron microscopy and the auger electron spectroscopy was used to analyze their surface morphology and basic structure. The Pd-black/NiCr gate MISFET has been shown high sensitivity and stability more than Pd-planar/NiCr gate MISFET.

PACVD of Plasma Polymerized Organic Thin Films and Comparison of their Electrochemical Properties

  • I.S. Bae;S.H. Cho;Kim, M.C.;Y.H. Roh;J.H. Boo
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2003.05a
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    • pp.53-53
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    • 2003
  • Plasma polymerized organic thin films were deposited on Si(100) glass and metal substrates using thiophene and ethylcyclohexane precursors by PECVD method. In order to compare electrochemical properties of the as-grown thin films, the effects of the RF plasma power in the range of 30~100 W. AFM showed that the polymer films with smooth surface and sharp interface could be grown under various deposition conditions. Impedance analyzer was utilized for the determination of I-V curve for leakage current density and C-V for dielectric constants, respectively. To obtain C-V curve, we used a MIM structure of metal(Al)-insulator(plasma polymerized thin film)-metal(Pt) structure. Al as the electrode was evaporated on the thiophene films that grew on Pt coated silicon substrates, and the dielectric constants of the as-grown films were then calculated from C- V data measured at 1MHz. From the electrical property measurements such as I-V and C-V characteristics, the minimum dielectric constant and the best leakage current of thiophene thin films were obtained to be about 3.22 and $1{\;}{\times}10^{-11}{\;}A/cm^2$. However, in case of ethylcyclohexane thin films, the minimum dielectric constant and the best leakage current were obtained to be about 3.11 and $5{\;}{\times}10^{-12}{\;}A/cm^2$.

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Improvement of dielectric and interface properties of Al/CeO$_2$/Si capacitor by using the metal seed layer and $N_2$ plasma treatment (금속씨앗층과 $N_2$ 플라즈마 처리를 통한 Al/CeO$_2$/Si 커패시터의 유전 및 계면특성 개선)

  • 임동건;곽동주;이준신
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.326-329
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    • 2002
  • In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

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Thickness Optimization of SiO2/Al2O3 Stacked Layer for High Performance pH Sensor Based on Electrolyte-insulator-semiconductor Structure (SiO2/Al2O3 적층 감지막의 두께 최적화를 통한 고성능 Electrolyte-insulator-semiconductor pH 센서의 제작)

  • Gu, Ja-Gyeong;Jang, Hyun-June;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.1
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    • pp.33-36
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    • 2012
  • In this study, the thickness effects of $Al_2O_3$ layer on the sensing properties of $SiO_2/Al_2O_3$ (OA) stacked membrane were investigated using electrolyte-insulator-semiconductor (EIS) structure for high quality pH sensor. The $Al_2O_3$ layers with a respective thickness of 5 nm, 15 nm, 23 nm, 50 nm, and 100 nm were deposited on the 5-nm-thick $SiO_2$ layers. The electrical characteristics and sensing properties of each OA membranes were investigated using metal-insulator-semiconductor (MIS) and EIS devices, respectively. As a result, the OA stacked membrane with 23-nm-thick $Al_2O_3$ layer shows the excellent characteristics as a sensing membrane of EIS sensor, which can enhance the signal to noise ratio.

Electron Emitter of Negative Electron Affinity Diamond

  • Hiraki, Akio;Ogawa, Kenji;Eimori, Nobuhiro;Hatta, Akimitsu
    • The Korean Journal of Ceramics
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    • v.2 no.4
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    • pp.193-196
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    • 1996
  • A new type of electron emitter device of chemical-vapor-deposited diamond thin film is proposed. The device is a diode of metal-insulator-insulator-semiconductor (MIS) structure consisting of an intrinsic polycrystalline diamond film as the insulator, an aluminium electrode on one side, and hydrogenated diamond surface on the other side as the p-type semconductor with negative electron affinity (NEA). Electrons will be injected and/or excited to the conduction band of intrinsic diamond layer to be emitted from the hydrogenated diamond surface of NEA.

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Electrical Properties of Metal-Ferroelectric-Insulator-Semiconductor Field-Effect Transistor Using an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si Structure

  • Jeon, Ho-Seung;Lee, Gwang-Geun;Kim, Joo-Nam;Park, Byung-Eun;Choi, Yun-Soo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.171-172
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    • 2007
  • We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

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Fabrications and properties of MFIS structure using AIN buffer layer (AIN 버퍼층을 사용한 MFIS 구조의 제작 및 특성)

  • 정순원;김용성;이남열;김진규;정상현;김광호;유병곤;이원재;유인규
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.29-32
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    • 2000
  • Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

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Analysis of A New Crossbar Embedded Structure for Improved Attenuation Characteristics on the Various Lossy Media (다양한 손실매질내의 손실특성 개선을 위한 새로운 크로스바 구조의 해석)

  • Kim, Yoon-Suk
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.12 s.354
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    • pp.83-88
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    • 2006
  • In this paper, we propose a new cross bar embedded structure for improvement of attenuation characteristics along the different lossy media. A general characterization procedure based on the extraction of the characteristic impedance and propagation constant for analyzing a single MIS(Metal-Insulator-Semiconductor) transmission line used and an analysis for a new substrate shielding MIS structure consisting of grounded crossbars at the interface between Si and Sio2 layer using the Finite-Difference Time-Domain(FDTD) technique is used. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded cross bar lines over time-domain signal has been examined. The extracted, distributed frequency-dependent transmission line parameters as well as the line voltages and currents, and also corresponding equivalent circuit parameters have been examined as function of frequency. It is shown that the quality factor of the transmission line can be improved without significant changes in the characteristic impedance and effective dielectric constant.

Effect of ${Y_2}{O_3}$Buffer Layer on the Characteristics of Pt/$YMnO_3$/$Y_2$$O_3$/Si(MFIS) Structure (Pt/$YMnO_3$/$Y_2$$O_3$/Si(MFIS) 구조의 특성에 미치는 ${Y_2}{O_3}$층의 영향)

  • Yang, Jeong-Hwan;Sin, Ung-Cheol;Choe, Gyu-Jeong;Choe, Yeong-Sim;Yun, Sun-Gil
    • Korean Journal of Materials Research
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    • v.10 no.4
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    • pp.270-275
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    • 2000
  • The Pt/YMnO$_3$/Y$_2$O$_3$/Si structure for metal/ferroelectric/insulator/semiconductor(MFIS)-FET was fabricated and effect of $Y_2$O$_3$layer on the properties of MFIS structure was investigated. The $Y_2$O$_3$ thin films on p-type Si(111) substrate deposited by Pulsed Laser Deposition were crystallized along (111) orientation irrespective of the deposition temperatures. Ferroelectric YMnO$_3$ thin films deposited directly on p-type Si (111) by MOCVD resulted in Mn deficient layer between Si and YMnO$_3$. However, YMnO$_3$ thin films having good quality and stoichiometric composition can be obtained by adopting $Y_2$O$_3$ buffer layer. The memory window of the $Y_2$O$_3$thin films with YMnO$_3$ film is greater than that of the YMnO$_3$ thin films without $Y_2$O$_3$ film after the annealing at 85$0^{\circ}C$ in vacuum ambient(100mtorr). The memory window is 1.3V at an applied voltage of 5V.

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