• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 지능정보연구
• /
• 제26권1호
• /
• pp.135-149
• /
• 2020

인공지능을 기반으로 한 다양한 연구들이 현대사회에 많은 변화를 불러일으키고 있다. 금융시장 역시 예외는 아니다. 로보어드바이저 개발이 활발하게 진행되고 있으며 전통적 방식의 단점을 보완하고 사람이 분석하기 어려운 부분을 대체하고 있다. 로보어드바이저는 인공지능 알고리즘으로 자동화된 투자 결정을 내려 다양한 자산배분 모형과 함께 활용되고 있다. 자산배분 모형 중 리스크패리티는 대표적인 위험 기반 자산배분 모형의 하나로 큰 자산을 운용하는 데 있어 안정성을 나타내고 현업에서 역시 널리 쓰이고 있다. 그리고 XGBoost 모형은 병렬화된 트리 부스팅 기법으로 제한된 메모리 환경에서도 수십억 가지의 예제로 확장이 가능할 뿐만 아니라 기존의 부스팅에 비해 학습속도가 매우 빨라 많은 분야에서 널리 활용되고 있다. 이에 본 연구에서 리스크패리티와 XGBoost를 장점을 결합한 모형을 제안하고자 한다. 기존에 널리 사용되는 최적화 자산배분 모형은 과거 데이터를 기반으로 투자 비중을 추정하기 때문에 과거와 실투자 기간 사이의 추정 오차가 발생하게 된다. 최적화 자산배분 모형은 추정 오차로 인해 포트폴리오 성과에서 악영향을 받게 된다. 본 연구는 XGBoost를 통해 실투자 기간의 변동성을 예측하여 최적화 자산배분 모형의 추정 오차를 줄여 모형의 안정성과 포트폴리오 성과를 개선하고자 한다. 본 연구에서 제시한 모형의 실증 검증을 위해 한국 주식시장의 10개 업종 지수 데이터를 활용하여 2003년부터 2019년까지 총 17년간 주가 자료를 활용하였으며 in-sample 1,000개, out-of-sample 20개씩 Moving-window 방식으로 예측 결과값을 누적하여 총 154회의 리밸런싱이 이루어진 백테스팅 결과를 도출하였다. 본 연구에서 제안한 자산배분 모형은 기계학습을 사용하지 않은 기존의 리스크패리티와 비교하였을 때 누적수익률 및 추정 오차에서 모두 개선된 성과를 보여주었다. 총 누적수익률은 45.748%로 리스크패리티 대비 약 5% 높은 결과를 보였고 추정오차 역시 10개 업종 중 9개에서 감소한 결과를 보였다. 실험 결과를 통해 최적화 자산배분 모형의 추정 오차를 감소시킴으로써 포트폴리오 성과를 개선하였다. 포트폴리오의 추정 오차를 줄이기 위해 모수 추정 방법에 관한 다양한 연구 사례들이 존재한다. 본 연구는 추정 오차를 줄이기 위한 새로운 추정방법으로 기계학습을 제시하여 최근 빠른 속도로 발전하는 금융시장에 맞는 진보된 인공지능형 자산배분 모형을 제시한 점에서 의의가 있다.