• Title/Summary/Keyword: memory yield

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Effect of Training( SIM↔γ) on Shape Memory Effect of Fe-30%Mn-6%Si Alloy (Fe-30%Mn-6% Si 합금의 형상기억효과에 미치는 Training(SIM↔γ)의 영향)

  • Han, Sang Ho;Jun, Joong Hwan;Choi, Chong Sool
    • Journal of the Korean Society for Heat Treatment
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    • v.7 no.2
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    • pp.118-128
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    • 1994
  • Five alloys were selected randomly in the composition range showing the best shape memory effect in Fe-Mn-Si system reported by Murakami. The shape memory effects of those alloys were mainly investigated through the training treatment which consisted of the repetition of 2% tensile deformation at room temperature and subsequent annealing at $600^{\circ}C$ above $A_r$ temperature. At the same deformation degress in rolling $600^{\circ}C$-annealing for 1 hr. showed the best shape memory effect, and 10%-deformation degrees represented maxima of the shpae memory effects at all annealing temperatures, $500^{\circ}C$, $600^{\circ}C$ and $700^{\circ}C$. The shape memory effects of the alloys were increased by increasing training cycle up to 5 cycles. This was because a large number of dislocations introduced by training process gave rise to increase in the austenite yield stress, and acted as nucleation sites for stress induced ${\varepsilon}$ martensite. The thermal cycling treatment, repetition of cooling in nitrogen at $-196{\circ}C$ and heating to $300^{\circ}C$ for 5 min., did not improve the shape memory effect.

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Searching Narrow Values of Cache Memory for Yield-Aware Cache Design under Process Variation (공정 변이 조건 하의 수율 인식 캐시 설계를 위한 캐시 메모리 내로우 밸류 검색)

  • Jang, Hyung-Beom;Chung, Sung-Woo;Yoon, Sung-Roh
    • Proceedings of the Korean Information Science Society Conference
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    • 2008.06b
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    • pp.456-459
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    • 2008
  • 공정 기술의 발전에 따라 공정 변이 (process variation)에 따른 수율 (yield) 감소 문제가 대두하고 있으며, 공정 변이 대응 설계 기법 (process variation tolerant design technique)은 하드웨어 제작 시 반드시 고려되어야 할 중요한 요소가 되었다. 캐시 메모리 (cache memory)의 경우에도 공정 변이로 인한 수율 감소 문제에 대처할 수 있는 설계 방법의 개발이 절실하다. 본 논문에서는 캐시에 저장되는 데이터의 특성 분석을 통해 공정 변이에 대응할 수 있는 새로운 캐시 구조 설계에 대한 연구를 소개한다.

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A Built-In Redundancy Analysis with a Minimized Binary Search Tree

  • Cho, Hyung-Jun;Kang, Woo-Heon;Kang, Sung-Ho
    • ETRI Journal
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    • v.32 no.4
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    • pp.638-641
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    • 2010
  • With the growth of memory capacity and density, memory testing and repair with the goal of yield improvement have become more important. Therefore, the development of high efficiency redundancy analysis algorithms is essential to improve yield rate. In this letter, we propose an improved built-in redundancy analysis (BIRA) algorithm with a minimized binary search tree made by simple calculations. The tree is constructed until finding a solution from the most probable branch. This greatly reduces the search spaces for a solution. The proposed BIRA algorithm results in 100% repair efficiency and fast redundancy analysis.

An Electrical Repair Circuit for Yield Increment of High Density Memory (고집적 메모리의 yield 개선을 위한 전기적 구제회로)

  • 김필중;김종빈
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.4
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    • pp.273-279
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    • 2000
  • Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

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A study on new control mechanisms of memory

  • Liu, Haibin;Kakazu, Yukinori
    • 제어로봇시스템학회:학술대회논문집
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    • 1992.10b
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    • pp.324-329
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    • 1992
  • A physical phenomenon is observed through analysis of the Hodgkin-Huxley's model that is, according to Maxwell field equations a fired neuron can yield magnetic fields. The magnetic signals are an output of the neuron as some type of information, which may be supposed to be the conscious control information. Therefore, study on neural networks should take the field effect into consideration. Accordingly, a study on the behavior of a unit neuron in the field is made and a new neuron model is proposed. A mathematical Memory-Learning Relation has been derived from these new neuron equations, some concepts of memory and learning are introduced. Two learning theorems are put forward, and the control mechanisms of memory are also discussed. Finally, a theory, i.e. Neural Electromagnetic(NEM) field theory is advanced.

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A Study of Establishment of Parameter and Modeling for Yield Estimation (수율 예측을 위한 변수 설정과 모델링에 대한 연구)

  • 김흥식;김진수;김태각;최민성
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.46-52
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    • 1993
  • The estimation of yield for semiconductor devices requires not only establishment of critical area but also a new parameter of process defect density that contains inspection mean defect density related cleanness of manufacure process line, minimum feature size and the total number of mask process. We estimate the repaired yield of memory devide, leads the semiconductor technique, repaired by redundancy scheme in relation with defect density distribution function, and we confirm the repaired yield for different devices as this model. This shows the possibility of the yield estimation as statistical analysis for the condition of device related cleanness of manufacture process line, design and manufacture process.

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Fully Room Temperature fabricated $TaO_x$ Thin Film for Non-volatile Memory

  • Choi, Sun-Young;Kim, Sang-Sig;Lee, Jeon-Kook
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.05a
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    • pp.28.2-28.2
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    • 2011
  • Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

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A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead

  • Yang, Myung-Hoon;Cho, Hyung-Jun;Jeong, Woo-Sik;Kang, Sung-Ho
    • ETRI Journal
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    • v.31 no.3
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    • pp.339-341
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    • 2009
  • Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

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RRAM (Redundant Random Access Memory) Spare Allocation in Semiconductor Manufacturing for Yield Improvement (수율향상을 위한 반도체 공정에서의 RRAM (Redundant Random Access Memory) Spare Allocation)

  • Han, Young-Shin
    • Journal of the Korea Society for Simulation
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    • v.18 no.4
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    • pp.59-66
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    • 2009
  • This has been possible by integration techniques such as very large scale integration (VLSI) and wafer scale integration (WSI). Redundancy has been extensively used for manufacturing memory chips and to provide repair of these devices in the presence of faulty cells. If there are too many defects, the momory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is nedded for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The proposed CRA (Correlation Repair Algorithm) simulation, beyond the idea of the conventional redundancy analysis algorithm, aims at reducing the time spent in the process and strengthening cost competitiveness by performing redundancy analysis after simulating each case of defect.

Level Shifts and Long-term Memory in Stock Distribution Markets (주식유통시장의 층위이동과 장기기억과정)

  • Chung, Jin-Taek
    • Journal of Distribution Science
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    • v.14 no.1
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    • pp.93-102
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    • 2016
  • Purpose - The purpose of paper is studying the static and dynamic side for long-term memory storage properties, and increase the explanatory power regarding the long-term memory process by looking at the long-term storage attributes, Korea Composite Stock Price Index. The reason for the use of GPH statistic is to derive the modified statistic Korea's stock market, and to research a process of long-term memory. Research design, data, and methodology - Level shifts were subjected to be an empirical analysis by applying the GPH method. It has been modified by taking into account the daily log return of the Korea Composite Stock Price Index a. The Data, used for the stock market to analyze whether deciding the action by the long-term memory process, yield daily stock price index of the Korea Composite Stock Price Index and the rate of return a log. The studies were proceeded with long-term memory and long-term semiparametric method in deriving the long-term memory estimators. Chapter 2 examines the leading research, and Chapter 3 describes the long-term memory processes and estimation methods. GPH statistics induced modifications of statistics and discussed Whittle statistic. Chapter 4 used Korea Composite Stock Price Index to estimate the long-term memory process parameters. Chapter 6 presents the conclusions and implications. Results - If the price of the time series is generated by the abnormal process, it may be located in long-term memory by a time series. However, test results by price fixed GPH method is not followed by long-term memory process or fractional differential process. In the case of the time-series level shift, the present test method for a long-term memory processes has a considerable amount of bias, and there exists a structural change in the stock distribution market. This structural change has implications in level shift. Stratum level shift assays are not considered as shifted strata. They exist distinctly in the stock secondary market as bias, and are presented in the test statistic of non-long-term memory process. It also generates an error as a long-term memory that could lead to false results. Conclusions - Changes in long-term memory characteristics associated with level shift present the following two suggestions. One, if any impact outside is flowed for a long period of time, we can know that the long-term memory processes have characteristic of the average return gradually. When the investor makes an investment, the same reasoning applies to him in the light of the characteristics of the long-term memory. It is suggested that when investors make decisions on investment, it is necessary to consider the characters of the long-term storage in reference with causing investors to increase the uncertainty and potential. The other one is the thing which must be considered variously according to time-series. The research for price-earnings ratio and investment risk should be composed of the long-term memory characters, and it would have more predictability.