• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.191-194
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• 2001

The availability of the inexpensive, large main memories coupled with the demand for faster response time are bringing a new perspective to database technology. The Web GIS used by u unspecified number of general public in the internet needs high speed response time and frequent data retrieval for spatial analysis rather than data update. Therefore, it is appropriate to use main memory as a underlying storage structures for the Web GIS data. In this paper, we propose a data representation method based on relative coordinates and the size of the MBR. The method is able to compress the spatial data widely used in the Web GIS into smaller volume of memory. We also propose a memory resident spatial index with simple mechanism for processing point and region queries. The performance test shows that the index is suitable for managing the skewed data in terms of the size of the index and the number of the MBR intersection check operations.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 1999.10a
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• pp.243-249
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• 1999

구매 의사 결정 과정에서 구매자는 상품 정보와 가격 정보를 필요로 한다. 웹상의 판매자 위주의 시장으로부터 필요한 정보를 수집하려면, 구매자는 매번 구매 때마다 판매자의 사이트를 검색해야 한다. 심지어 구매자가 거래하고 있는 판매자로부터 과거에 구매한 경험이 있는 아이템을 구매하는 경우에도 마찬가지이다. 현재의 전자상거래 환경에서는, 이렇게 기억을 활용하지 않고(memory-less) 검색에만 의존하는 구매자의 행태가 일반적이다. 이 현상을 조직의 구매 경험이 구성원들에게 공유되어야 하는 기업 구매자의 경우에 있어서는 대단히 낭비적인 요소로 작용될 것이다. 구매자 에이전트에게 기억 능력을 부여하려면, 구매자 에이전트와 판매자 에이전트가 갖고 있는 정보간의 일관성을 유지해 주어야 할 필요가 있다. 최소의 노력으로 일관성을 유지하려면, 구매자 에이전트와 판매자 에이전트간에 체계적인 갱신 프로토콜이 필요하다. 본 연구에서는 6가지의 프로토콜(Instantaneous Pull, Periodic Pull, Instantaneous Push, Periodic Push, Instantaneous Solicited Push, Periodic Solicited Push)을 비교하고, 에이전트의 아키텍처와 KQML/XML에 기반 한 메시지 구조를 제시한다. 이들 프로토콜의 상황에 따른 수행 성능 평가가 진행 중이며, 이러한 상황에 적응할 수 있는 에이전트의 프로토타입이 현재 개발 중이다.

• Nuclear Engineering and Technology
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• v.52 no.11
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• pp.2667-2677
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• 2020

A domain decomposition (DD) scheme for GPU-based Monte Carlo (MC) calculation which is essential for whole-core depletion is introduced within the framework of the modified history-based tracking algorithm. Since GPU-offloaded MC calculations suffer from limited memory capacity, employing DDMC is inevitable for the simulation of depleted cores which require large storage to save hundreds of newly generated isotopes. First, an automated domain decomposition algorithm named wheel clustering is devised such that each subdomain contains nearly the same number of fuel assemblies. Second, an innerouter iteration algorithm allowing overlapped computation and communication is introduced which enables boundary neutron transactions during the tracking of interior neutrons. Third, a bank update scheme which is to include the boundary sources in a way to be adequate to the peculiar data structures of the GPU-based neutron tracking algorithm is presented. The verification and demonstration of the DDMC method are done for 3D full-core problems: APR1400 fresh core and a mock-up depleted core. It is confirmed that the DDMC method performs comparably with the standard MC method, and that the domain decomposition scheme is essential to carry out full 3D MC depletion calculations with limited GPU memory capacities.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.7B
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• pp.818-826
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• 2011

This paper proposes a novel FTL (Flash Translation Layer) algorithm employing sector-level mapping technique based on locality to reduce the number of erase operations in flash memory accesses. Sector-level mapping technique shows higher performance than other mapping techniques, even if it requires a large mapping table. The proposed algorithm reduces the size of mapping table by employing dynamic table update, processes sequential writes by exploiting sequential locality and extracts hot sector in random writes. Experimental results show that the number of erase operations has been reduced by 75.4%, 65.8%, and 10.3% respectively when compared with well-known BAST, FAST and sector mapping algorithms.

• Journal of the Korea Society of Computer and Information
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• v.20 no.6
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• pp.1-11
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• 2015

Recently, NAND flash memories are used for storage devices because of fast access speed and low-power. However, applications of FTL on low power computing devices lead to heavy workloads which result in a memory requirement and an implementation overhead. Consequently, studies of B+-Tree on embedded devices without the FTL have been proposed. The studies of B+-Tree are optimized for performance of inserting and updating records, considering to disadvantages of the NAND flash memory that it can not support in-place update. However, if a general garbage collection method is applied to the previous studies of B+-Tree, a performance of the B+-Tree is reduced, because it generates a rearrangement of the B+-Tree by changing of page positions on the NAND flash memory. Therefor, we propose a novel garbage collection method which can apply to the B+-Tree based on the NAND flash memory without the FTL. The proposed garbage collection method does not generate a rearrangement of the B+-Tree by using a block information table and a proxy block. We implemented the B+-Tree and ${\mu}$-Tree with the proposed garbage collection on physical devices with the NAND flash memory. In experiment results, the proposed garbage collection scheme compared to greedy algorithm garbage collection scheme increased the number of inserted keys by up to about 73% on B+-Tree and decreased elapsed time of garbage collection by up to about 39% on ${\mu}$-Tree.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.1-10
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• 2010

Recently heterogeneous storage system such as hybrid hard disk drive (H-HDD) combining flash memory and magnetic disk is launched, according as the read performance of NAND flash memory is enhanced as similar to that of hard disk drive (HDD) and the power consumption of NAND flash memory is reduced less than that of HDD. However, the read and write operations of NAND flash memory are slower than those of rotational disk. Besides, serious overheads are incurred on CPU and main memory in the case that intensive write requests to flash memory are repeatedly occurred. In this paper, we propose the Least Frequently Used-Hot scheme that replaces the data blocks whose reference frequency of read operation is low and update frequency of write operation is high, and the data flushing scheme that rearranges the data blocks into the multi-zone of the rotation disk. Experimental results show that the execution time of the proposed method is 38% faster than those of conventional LRU and LFU block replacement schemes in I/O performance aspect and the proposed method increases the life span of Non-Volatile Cache 40% higher than those of conventional LRU, LFU, FIFO block replacement schemes.

• The Journal of the Korea Contents Association
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• v.16 no.8
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• pp.706-716
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• 2016

Because of efficient space utilization and fast key search times, B-trees have been widely accepted for the use of indexes in HDD-based DBMSs. However, when the B-ree is stored in flash memory, its costly operations of node updates may impair the performance of a DBMS. This is because the random updates in B-tree's leaf nodes could tremendously enlarge I/O costs for the garbage collecting actions of flash storage. To solve the problem, we make all the parents of leaf nodes the virtual nodes, which are not stored physically. Rather than, those nodes are dynamically generated and buffered by referring to their child nodes, at their access times during key searching. By performing node updates and tree reconstruction within a single flash block, our proposed B-tree can reduce the I/O costs for garbage collection and update operations in flash. Moreover, our scheme provides the better performance of key searches, compared with earlier flash-based B-trees. Through a mathematical performance model, we verify the performance advantages of the proposed flash B-tree.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.545-550
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• 2018

Ultra-lightweight block cipher CHAM, consisting of simple addition, rotation, and eXclusive-or operations, enables the efficient implementations over both low-end and high-end Internet of Things (IoT) platforms. In particular, the CHAM block cipher targets the enhanced computational performance for the low-end IoT platforms. In this paper, we introduce the efficient implementation techniques to minimize the memory consumption and optimize the execution timing over 8-bit AVR IoT platforms. To achieve the higher performance, we exploit the partly iterated expression and arrange the memory alignment. Furthermore, we exploit the optimal number of register and data update. Finally, we achieve the high RANK parameters including 29.9, 18.0, and 13.4 for CHAM 64/128, 128/128, and 128/256, respectively. These are the best implementation results in existing block ciphers.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.5
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• pp.322-330
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• 2009

In order to utilize NAND flash memory as storage media which does not allow update-in-place and limits the number of block erase count, various garbage collection policies supporting wear-leveling have been investigated. Conventional garbage collection policies require cleaning-index calculation for the entire blocks to choose a block to be garbage-collected to support wear-leveling whenever a garbage collection is required, which results in performance degradation of system. This paper proposes a garbage collection policy which supports wear-leveling using a threshold value, which is in fact a variance of erase counts and by the maximum erase count of all blocks, without calculating the cleaning-index. During garbage collection, the erase cost is minimized by using the Greedy Policy if the variance is less than the threshold value. It achieves wear-leveling by excluding the block with the largest erase count from erase target blocks if the variance is larger than threshold value. The proposed scheme shows that a standard deviation approaches to zero as the erase count of blocks approaches to its upper limit and the measured speed of garbage collection is two times faster than the conventional schemes.