• 제목/요약/키워드: memory load

검색결과 341건 처리시간 0.024초

미시역학적 접근에 의한 단결정 형상기억합금의 리오리엔테이션 거동 모델링 (Modeling of the Reorientation Behavior of a Single Crystalline Shape- Memory Alloy by a Micromechanical Approach)

  • 구병춘
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2000년도 춘계학술대회 논문집
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    • pp.250-257
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    • 2000
  • A Helmholtz free energy for a martensitic transformation of a single crystalline shape-memory alloy is obtained by a micromechanical approach, 24 variants of the single crystal are taken into account. In the framework of irreversible thermodynamics, a kinetic relation, a martensitic nucleation criterion and the reorientation criterion of martensitic variants are obtained. These relations are valid for a three-dimensional proportional or non-proportional mechanical loading or a combination of mechanical and thermal loading. Reorientation behavior of a single crystalline shape-memory alloy CuZnAl is simulated. When a tensile load is applied to a thermally-induced martensite, 24 self-accommodated martensitic variants are reoriented to the most favorable variant. In the following unloading, the most favorable variant in the tensile load is reoriented to the most favorable variant in this loading condition.

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조현병 및 정신증 고위험군에서의 작업기억 손상 (Working Memory Deficits in Ultra-High Risk for Psychosis and Schizophrenia)

  • 전임홍;박종석;박진영;조혜현;구세준;이은;안석균;유선국
    • 대한조현병학회지
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    • 제15권2호
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    • pp.66-72
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    • 2012
  • Objectives : The aim of this study was to investigate whether verbal and spatial working memory functions were impaired not only in patients with schizophrenia but also in people at ultra-high risk for first-episode psychosis. Methods : Twenty-five patients (M 13, F 12) with schizophrenia (SPR), 21 people at ultra-high risk for psychosis (UHR)(M 10, F 11) and 19 normal controls (NC)(M 10, F 9) were recruited. The working memory was assessed by using the verbal and spatial n-back test. The working memory load increased incrementally from the 0-back to the 3-back condition. Results : SPR performed significantly lower than NC and UHR in terms of hit rates of verbal and spatial n-back test. UHR subjects conducted significantly lower than NC and higher in trend-level than SPR in terms of hit rates of verbal and spatial n-back test. These differences were derived from the high working memory load (2-back and 3-back), not from the low working memory load (0-back and 1-back). There was no significant difference between the verbal and spatial n-back test across the three groups. Conclusion : These findings suggest that verbal and spatial working memory dysfunction may be general rather than differential in terms of stimuli modality, and this working memory deficit may be an important trait factor in schizophrenia.

Bending and buckling analysis of sandwich Reddy beam considering shape memory alloy wires and porosity resting on Vlasov's foundation

  • Bamdad, Mostafa;Mohammadimehr, Mehdi;Alambeigi, Kazem
    • Steel and Composite Structures
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    • 재36권6호
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    • pp.671-687
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    • 2020
  • The aim of this research is to analyze buckling and bending behavior of a sandwich Reddy beam with porous core and composite face sheets reinforced by boron nitride nanotubes (BNNTs) and shape memory alloy (SMA) wires resting on Vlasov's foundation. To this end, first, displacement field's equations are written based on the higher-order shear deformation theory (HSDT). And also, to model the SMA wire properties, constitutive equation of Brinson is used. Then, by utilizing the principle of minimum potential energy, the governing equations are derived and also, Navier's analytical solution is applied to solve the governing equations of the sandwich beam. The effect of some important parameters such as SMA temperature, the volume fraction of SMA, the coefficient of porosity, different patterns of BNNTs and porous distributions on the behavior of buckling and bending of the sandwich beam are investigated. The obtained results show that when SMA wires are in martensite phase, the maximum deflection of the sandwich beam decreases and the critical buckling load increases significantly. Furthermore, the porosity coefficient plays an important role in the maximum deflection and the critical buckling load. It is concluded that increasing porosity coefficient, regardless of porous distribution, leads to an increase in the critical buckling load and a decrease in the maximum deflection of the sandwich beam.

Assessment of long-term working memory by a delayed nonmatch-to-place task using a T-maze

  • Kim, Jung-Eun;Choi, Jun-Hyeok;Kaang, Bong-Kiun
    • Animal cells and systems
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    • 제14권1호
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    • pp.11-15
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    • 2010
  • Long-term working memory (LTWM) is a subdivision concept of working memory and indicates the enhancement of performance in a working memory task. LTWM has been shown in humans who have been engaged in a specific task requiring working memory over a long time. However, there is very little understanding of the exact mechanism of LTWM because of limitations of experimental methods in human studies. We have modified the standard T-maze task, which is used to test working memory in mice, to demonstrate LTWM in an animal model. We observed an enhancement of performance by repeated experience with the same working memory load in mice, which can be regarded as an LTWM. This effect seems to depend on the condition wherein a delay was given. This task may be a good experimental protocol to assess LTWM in animal studies.

소형 digital computer를 이용한 대전력계통의 해석 (Analysis of Large Power System by Small Digital Computer)

  • 박영문;정재길
    • 전기의세계
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    • 제23권1호
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    • pp.61-68
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    • 1974
  • This paper attempts to develop the algorithms and computer program for load flow solution and faults analysis of large power system by small digital computer. The Conventional methods for load flow solution and fault analysis of large power system require too much amount of computer memory space and computing time. Therefore, this paper describes the methad for reducing the computer memory space and computing time as follows. (1) Load Flow Solution; This method is to store each primitive impedance of lines along with a list of bus numbers corresponding to the both terminals of lines, and to store only nonzero element of bus admittance matrix. (2) Faults Analysis: This method is to partition a large power system into several groups of subsystems, form individual bus impedance matrix, store them in the storage, and assemble the only required portion of them to original total system by algorithm.

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Distributed memory access architecture and control for fully disaggregated datacenter network

  • Kyeong-Eun Han;Ji Wook Youn;Jongtae Song;Dae-Ub Kim;Joon Ki Lee
    • ETRI Journal
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    • 제44권6호
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    • pp.1020-1033
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    • 2022
  • In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 ㎲. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 ㎲. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 ㎲ for all MI traffic with less than 10% of transmission overhead.

Intelligent한 메모리 시스템에서의 Fine-Grained SW Offloading을 위한 성능 분석 (Performance Analysis for Fine-Grained SW Offloading in Intelligent Memory System)

  • 허인구;김용주;이진용;이지훈;이종원;백윤흥
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2012년도 춘계학술발표대회
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    • pp.29-32
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    • 2012
  • 전통적으로 컴퓨터의 성능은 중앙 연산 장치 (CPU)의 성능에 따라 좌지우지 되어 왔다. 하지만 CPU의 성능이 지속적인 발전을 거듭하여 무어의 법칙을 비교적 충실히 따라가고 있는 반면, 메모리의 성능은 근래 들어 더디게 발전되는 형국이다. 때문에, CPU와 메모리 간의 성능격차로 인해 메모리의 낮은 성능이 전체 시스템의 성능을 저하시키는 "Memory Wall Problem"은 점점 큰 문제로 대두되고 있다. 이러한 문제를 해결하기 위해 많은 연구에서 메모리 자체의 성능을 발전시키는 것은 물론 메모리 내부에 연산 처리 능력을 추가하여 시스템 전체의 성능을 향상 시키는 시도들을 해왔다. 이 논문에서는 이러한 Intelligent한 메모리 시스템에서의 SW Off-loading을 위한 성능 분석을 다룬다. 이전의 연구들이 주로 큰 단위의 Off-load를 다뤘던 것에 비해 이 논문에서는 작은 단위의 Off-load, 더 정확히는 어셈블리 수준의 Off-load의 효과에 대해 분석한다. 또한 현재의 어셈블리 수준의 Off-load의 한계를 지적하고 이를 극복하기 위한 루프 레벨 Off-load, 새로운 Technology와 아키텍쳐에 대해서도 소개한다.

내장형 시스템을 위한 PMU (Performance Monitoring Unit) 기반 동적 XIP (eXecute In Place) 기법 ((PMU (Performance Monitoring Unit)-Based Dynamic XIP(eXecute In Place) Technique for Embedded Systems))

  • 김도훈;박찬익
    • 대한임베디드공학회논문지
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    • 제3권3호
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    • pp.158-166
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    • 2008
  • These days, mobile embedded systems adopt flash memory capable of XIP feature since they can reduce memory usage, power consumption, and software load time. XIP provides direct access to ROM and flash memory for processors. However, using XIP incurs unnecessary degradation of applications' performance because direct access to ROM and flash memory shows more delay than that to main memory. In this paper, we propose a memory management framework, dynamic XIP, which can resolve the performance degradation of using XIP. Using a constrained RAM cache, dynamic XIP can dynamically change XIP region according to page access pattern to reduce performance degradation in execution time or energy consumption resulting from native XIP problem. The proposed framework consists of a page profiler gathering applications' memory access pattern using PMU and an XIP manager deciding that a page is accessed whether in main memory or in flash memory. The proposed framework is implemented and evaluated in Linux kernel. Our evaluation shows that our framework can reduce execution time at most 25% and energy consumption at most 22% compared with using XIP-only case adopted in general mobile embedded systems. Moreover, the evaluation shows that in execution time and energy consumption, our modified LRU algorithm with code page filters can reduce more than at most 90% and 80% respectively compared with applying just existing LRU algorithm to dynamic XIP.

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CNN 가속기의 효율적인 데이터 전송을 위한 메모리 데이터 레이아웃 및 DMA 전송기법 연구 (Memory data layout and DMA transfer technique research For efficient data transfer of CNN accelerator)

  • 조석재;박성경;박성정
    • 전기전자학회논문지
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    • 제24권2호
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    • pp.559-569
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    • 2020
  • 딥 러닝 알고리즘 중 하나인 CNN 인공지능 어플리케이션은 하드웨어 측면에서 컨벌루션 레이어의 많은 데이터들을 저장하기 위해 오프 칩 메모리를 사용 하고, DMA를 사용하여 매 데이터 전송 시 프로세서의 부하를 줄여 성능을 향상 시킬 수 있다. 또한 컨벌루션 레이어의 데이터를 가속기의 글로벌 버퍼에 전송되는 순서를 다르게 하여 어플리케이션의 성능의 저하를 줄일 수 있다. 불 연속된 메모리 주소를 가지고 있는 베이직 레이아웃의 경우 SG-DMA를 사용 할 때 ordinary DMA를 사용할 때보다 DMA를 사전 설정하는 부분에서 약 3.4배의 성능향상을 보였고 연속적인 메모리 주소를 가지고 있는 아이디얼 레이아웃의 경우 ordinary DMA 와 SG-DMA를 사용하는 두가지 경우 모두 1396 사이클 정도의 오버헤드를 가졌다. 가장 효율적인 메모리 데이터 레이아웃과 DMA의 조합은 프로세서의 DMA 사전 설정 부하를 약 86 퍼센트까지 감소할 수 있음을 실험을 통해 확인했다.

복수 메모리 타일을 가진 NoC 매니코어 플랫폼에서의 태스크-타일 바인딩 기술 (Task-to-Tile Binding Technique for NoC-based Manycore Platform with Multiple Memory Tiles)

  • 강진택;김태영;김성찬;하순회
    • 정보과학회 논문지
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    • 제43권2호
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    • pp.163-176
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    • 2016
  • NoC 아키텍쳐에서는 데이터의 통신이 한 채널에 집중되는 경우 경합이 일어나서 통신이 지연될 수 있다. 이러한 지연을 최소화시키는 것을 목표로 본 논문에서는 NoC 기반 매니코어 플랫폼에서 태스크 매핑이 완료된 이후, 매핑된 태스크들을 NoC 타일로 바인딩하기 위한 기법을 제안한다. 큰 규모의 플랫폼은 복수의 메모리 타일을 가질 수 있으므로 응용별로 사용하는 메모리를 다르게 하여 메모리별 부하를 분산시키기 위한 메모리 클러스터링 기법을 사용한다. 수행된 응용은 데이터플로우 기반으로 작성되어 있으므로 응용들의 통신 요구량에 대한 정보를 미리 알 수 있다고 가정한다. 이 정보를 바탕으로 본 논문에서는 여러 태스크를 동시에 바인딩하는 두개의 휴리스틱을 제안하였으며 각 휴리스틱은 적절한 메모리 클러스터링 기법을 활용한다. NoC 시뮬레이터를 이용한 실험을 통해 제안된 휴리스틱이 기존의 바인딩 휴리스틱에 비해 최대 25% 이상의 성능을 보이는 것을 확인하였다.