• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.161-186
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• 2012

Recently, the flash memory consistently increases the storage capacity while the price of the memory is being cheap. This makes the mass storage SSD(Solid State Drive) popular. The flash memory, however, has a lot of defects. In order that these defects should be complimented, it is needed to use the FTL(Flash Translation Layer) as a special layer. To operate restrictions of the hardware efficiently, the FTL that is essential to work plays a role of transferring from the logical sector number of file systems to the physical sector number of the flash memory. Especially, the poor performance is attributed to Erase-Before-Write among the flash memory's restrictions, and even if there are lots of studies based on the log block, a few problems still exists in order for the mass storage flash memory to be operated. If the FAST based on Log Block-Based Flash often is generated in the wide locality causing the random writing, the merge operation will be occur as the sectors is not used in the data block. In other words, the block thrashing which is not effective occurs and then, the flash memory's performance get worse. If the log-block makes the overwriting caused, the log-block is executed like a cache and this technique contributes to developing the flash memory performance improvement. This study for the improvement of the random writing demonstrates that the log block is operated like not only the cache but also the entire flash memory so that the merge operation and the erase operation are diminished as there are a distinct mapping table called as the offset mapping table for the operation. The new FTL is to be defined as the XAST(extensively-Associative Sector Translation). The XAST manages the offset mapping table with efficiency based on the spatial locality and temporal locality.

• Journal of Broadcast Engineering
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• v.19 no.2
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• pp.227-239
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• 2014

This paper proposes an enhance prediction for conventional near-lossless coder to effectively lower external memory bandwidth in image processing SoC. First, we utilize an already reconstructed green component as a base of predictor of the other color component because high correlation between RGB color components usually exists. Next, we can improve prediction performance by applying variable block size prediction. Lastly, we use minimum internal memory and improve a temporal prediction performance by using a template dictionary that is sampled in previous frame. Experimental results show that the proposed algorithm shows better performance than the previous works. Natural images have approximately 30% improvement in coding efficiency and CG images have 60% improvement on average.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.471-474
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• 2012

The administration of government agencies and Law enforcement agencies is utilize. that network separation and Establish CERT for network security. However, the legislature has a basic security system. so a lot of relative vulnerability. In this paper, study for security National Assembly and the National Assembly Secretariat, at Library of National Assembly on legislative National Assembly for information security and network configuration, network and external Internet networks is to divide the internal affairs. Network separation in accordance with the movement of materials to use secure USB memory, the user has the uncomfortable issues. Problem analysis and security vulnerabilities on the use of USB memory is study the problem. User efficiency and enhance security.

• Journal of Digital Contents Society
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• v.19 no.4
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• pp.757-770
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• 2018

Foreground extraction is the most significant step in thermal imaging based surveillance systems. This step needs to be efficient in terms of time and memory consumption in order for the system to provide real time results but usually this efficiency reciprocates with the accurateness of the ROI detection. In this study, novel selective histogram bins based two background & foreground separation approaches for thermal videos processing have been proposed which exploit the temporal-consistency property of the thermal images in a given environment and can save over 80% memory than their simplest counterpart temporal median filtering.

• Journal of Korean Society of Transportation
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• v.22 no.5
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• pp.61-73
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• 2004

The efficiency of the real-time route guidance system(RGS) depends largely on the quality of route search algorithms. In this paper, we implement the coarse grid method(CGM) in mathematical programming for finding a good quality route of real-time RGS in large-scale networks. The proposed CGM examines coarser and wider networks as the search phase proceeds, in stead of searching the whole network at once. Naturally, we can significantly reduce computational efforts in terms of search time and memory requirement. We demonstrate the practical effectiveness of the proposed CGM with nationwide real road network simulation.

• Korean Institute of Interior Design Journal
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• v.20 no.1
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• pp.138-145
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• 2011

This study analyzed the time to understand the space and the contents of information to be memorized in the indoor space. Understanding the space and examining the memory will not only provide the basic data on which visual activities occur in user's perceiving the designed space but also expand the activity range of interior designer. The summary of the study results is as follows: First, with respect to gender difference, the results showed that males grasped the space in a relatively shorter time. Females showed more concentrated distribution range than males. Second, as for the proper time by accumulative sum across time, the results showed that it increased continuously until V time zone(120~150 seconds), it decreased rapidly after the V zone, which indicated that the proper gazing time for the indoor space as the target of this study is less than 150 seconds(effective gazing time). Third, in terms of efficiency of information acquisition, the results suggested that "60~90 seconds" are the effective time for acquiring the greatest amount of information. Fourth, regarding the information acquisition method, males were approximately 4.1%~0.1% lower in the evaluation through phrase and image. The evaluation of subjects through phrase than image was connected to more accurate information acquisition.

• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• Journal of KIISE:Software and Applications
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• v.37 no.9
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• pp.669-675
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• 2010

For detecting requirement errors in early system development phase, the behaviors of a system should be described in formal methods and be analyzed with analysis techniques such as reachability analysis and cycle detection. However, since they are usually based on explicit exploration of system state space, state explosion problem may be occurred when a system becomes complex. That is, the memory and execution time for exploration exponentially increase due to a huge state space. In this paper, we analyze the fundamental causes of this problem in concurrent systems and explore the state space without composing concurrent state spaces for reducing the memory requirement for exploration. Also our new technique keeps a visited history minimally for reducing execution time. Finally we represent experimental results which show the efficiency of our technique.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Journal of Korea Game Society
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• v.19 no.6
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• pp.91-98
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• 2019

This study verified the memory occupancy, CPU processing speed, and average frame comparison of texture formats of ASTC and ETC in mobile Android OS. The virtual game scene was implemented as an experimental environment and built on the Android platform. Based on this, comparative verification data was extracted. ASTC has a 36% lower share of memory usage of 2D textures than ETC. CPU processing speed was 18% faster. The average frame confirmed 54 frames that was 58% higher. In the smart mobile game environment, ASTC confirmed the result of comparative advantage over ETC.