• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.675-688
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• 2007

Memory access errors are frequently occurred in C programs. A number of tools and research works have been trying to detect the errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, incompatibility with libraries, and excessive performance overhead. In this paper, we suggest a new method to solve these problems, and then present a result of comparison to the previous research works through the experiments. Our approach consists of two phases. First is to transform source code at compile time through inserting instrumentation into the source code. And second is to detect memory errors at run time with a bitmap that maintains information about memory allocation. Our approach has improved the error detection abilities against the binary code analysis based ones by using the source code analysis technique, and enhanced performance in terms of both space and time, too. In addition, our approach has no problem with respect to compatibility with shared libraries as well as does not need to modify memory allocation mechanism.

• Journal of Korea Multimedia Society
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• v.16 no.8
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• pp.914-926
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• 2013

Among the recent security systems, security system with fingerprint recognition gets many people's interests through the strengths such as exclusiveness, convenience, etc, in comparison with other security systems. The most important matters for fingerprint recognition system are reliability of matching between the fingerprint in database and user's fingerprint and rapid process of image processing algorithms used for fingerprint recognition. The existing fingerprint recognition system reduces the processing time by removing some processes in the feature extraction algorithms but has weakness of a reliability. This paper realizes the fingerprint recognition algorithm using MAMS(Multi-Access Memory System) for both the rapid processing time and the reliability in feature extraction and matching accuracy. Reliability of this process is verified by the correlation between serial processor's results and MAMS-PP64's results. The performance of the method using MAMS-PP64 is 1.56 times faster than compared serial processor.

• KIISE Transactions on Computing Practices
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• v.21 no.8
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• pp.543-548
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• 2015

Recently, volume of data has been growing dramatically along with the growth of social media and digital devices. However, the existing disk-based distributed file systems have limits to their performance of data processing or data access, due to I/O processing costs and bottlenecks. To solve this problem, the caching technique is being used to manage data in the memory. In this paper, we propose a cache management scheme to handle load balancing in a distributed memory environment. The proposed scheme distributes the data according to the memory size, n distributed environments with different memory sizes. If overloaded nodes occur, it redistributes the the access time of the caching data. In order to show the superiority of the proposed scheme, we compare it with an existing distributed cache management scheme through performance evaluation.

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Journal of the Korea Society for Simulation
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• v.2 no.1
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• pp.13-22
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• 1993

In a multiple-bus multiprocessor system in which processors and memory modulus are interconnected through system buses, time delay due to bus contention degrades system performance. In order to reduce such a problem , and optimal bus arbitration scheme and its hardware are neccessary. In this study, performaces of four arbitration schemes are analyzed and compared : fixed-priority, equal-priority, rotating-priority and round-robin priority schemes. For the study, the software simulator of a multiple-bus multiprocessor system is developed by using SLAM II. Simulation results show that, when memory sccesses are evenly distributed to all memory modulus, round-robin priority scheme provides the best performance. But when a hot spot exists, the use of the fixed priority scheme results in the shortest access time.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1753-1765
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• 2000

As the areas of computer application are expanded, real-time application environments that must process as many transactions as possible within their deadlines, such as a stock transaction systems, ATM switching systems etc, have been increased recently. The reason why the conventional database systems can't process soft real-time applications is the lack of prediction and poor performance on processing transaction's deadline. If transactions want to access data stored at the secondary storage, they can not satisfy requirements of real-time applications because of the disk delay time. This paper designs a main-memory database prototype systems to be suitable to real-time applications and then this system can produce rapid results without disk i/o as all of the information are loaded in main memory database. In thesis proposed the improved techniques with respect to logging, checkpointing, and recovering in our environment. In order to improve the performance of the system, a) the frequency of log analysis and redo processing is reduced by the proposed redo technique at system failure, b) database consistency is maintained by improved fuzzy checkpointing. The performance model is proposed which consists of two parts. The first part evaluates log processing time for recovery and compares with other research activities. The second part examines checkpointing behavior.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.399-404
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• 2002

Along the evolution of information and communication technologies, manufacturing embedded systems such as PDA (personal digital assistant), HPC (hand -held PC), settop box. and information appliance became realistic. And RTOS (real-time operating system) and filesystem have been played essential re]os within the embedded systems as well. For the filesystem of embedded systems, flash memory has been used extensively instead of traditional hard disk drives because of embedded system's requirements like portability, fast access time, and low power consumption. Other than these requirements, nonvolatile storage characteristic of flash memory is another reason for wide adoption in industry. However, there are some technical challenges to cope with to use the flash memory as an indispensable component of the embedded systems. These would be relatively slow cleaning time and the limited number of times to write-and-clean. In this paper, a new cleaning policy is proposed to overcome the problems mentioned above and relevant performance comparison results will be provided. Ranking cleaning policy(RCP) decides when and where to clean within the flash memory considering the cost of cleaning and the number of times of cleaning. This method will maximize not only the lifetime of flash memory but also the performance of access time and manageability. As a result of performance comparison, RCP has showed about 10 ~ 50% of performance evolution compared to traditional policies, Greedy and Cost-benefit methods, by write throughputs.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.98-101
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• 2002

This paper reports a parallel architecture in a HMM based speech recognition system for a low-power LSI design. The proposed architecture calculates output probability of continuous HMM (CHMM) by using concurrent and pipeline processing. They enable to reduce memory access and have high computing efficiency. The novel point is the efficient use of register arrays that reduce memory access considerably compared with any conventional method. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.

• Journal of Korea Game Society
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• v.20 no.5
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• pp.89-98
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• 2020

In MMO game servers, NUMA (Non-Uniform Memory Access) architecture is generally used to achieve high performance. Furthermore, such servers normally use hash tables as internal data structure which have constant time complexity for insert, delete, and search operations. In this study, we proposed a concurrent hash table optimized for NUMA system to make MMO game servers improve their performance. We tested our hash table on 4 socket NUMA system, and the hash table shows at most 100% speedup over another high-performance hash table.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.757-767
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• 1995

In this paper, we present MI-MESI write-invalidate snooping cache coherence protocol which addresses several significant drawbacks of MESI and MI-MESI write -invalidate snooping cache coherence protocols under the split transaction bus based multiprocessor environment. In this protocol, each cache block maintains one of six cache states which represent Modified-shared, Invalid-by-other, Modified, Exclusive, Shared and Invalid states. By using these cache states, our protocol reduces both the access contention and unnecessary updates for the memory modules significantly, and thus providing the fast memory access time.