• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.103-104
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• 2006

PRAM (Phase change Random Access Memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change material has been researched in the field of optical data storage media. However, the characteristics required in solid state memory are quite different from optical ones. In this study, the reset current and temperature profile of PRAM cells with bottom electrode were calculated by the numerical method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.368-369
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• 2006

Ferroelectric thin films have attracted much attention for applications in nonvolatile ferroelectric random access memories(NVFeRAM) from the view points of high speed operation, low power consumption, and large scale Integration[1,2]. Among the FRAM, BLT is of particular interest. as it is not only crystallized at relatively low processing temperature, but also shows highly fatigue resistance and large remanent polarization Meanwhile, these submicron ferroelectric capacitors were fabricated by a damascene process using Chemical mechanical polishing (CMP). BLT capacitors were practicable by a damascene process using CMP. The P-E hysteresis were measured under an applied bias of ${\pm}5V$ by using an RT66A measurement system. The electric properties such as I-V were determined by using HP4155A analysers.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.81-92
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• 1995

In this paper, we present a high-level synthesis system that generates area-efficient RT-level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. Experimental results show the effectiveness of the proposed algorithm. When compared with previous approaches for several benchmarks available from literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.177-185
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• 1996

This paper describes several algorithms for technolgoy mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improved the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as merging fanin, unified reduction and multiple disjoint decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Korean Journal of Computational Design and Engineering
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• v.2 no.3
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• pp.161-174
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• 1997

In this paper, the techniques for graphic simulation of material removal process are described. The concepts of the bounding box and base plane are proposed. With these concepts, a real-time shaded display of a Z-map model being milled by a cutting tool following an NC path can be implemented very efficiently. The base planes make it possible to detect the visible face of Z-map model effectively. And the bounding box of tool sweep volume provides minimum area of screen to be updated. The proposed techniques are suitable for implementation in raster graphic device and need a few memories and a small amount of calculation. Proposed method is written in C and executable on MS-Windows95 and Window-NT.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.173-179
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• 2012

In this paper, we propose an efficient architecture for 2D IWT using an existing 1D IWT. Lifting based IWT is the architecture of which a multiplier is replaced by adders and shift registers. The structure is relatively simple and modular. The proposed architecture to process an image size with 256x256 pixels consists of 16 adders, 8 shift registers, and some memories. By processing two rows at the same time, 2D sub-band coefficients can be calculated immediately after 1D sub-band coefficients have been processed. The architecture is designed so that each image can be inputted consecutively. The number of adders and shift registers is increased by twice comparing the existing architecture, but the memory size and the execution time are decreased by half. The proposed architecture is implemented using Verilog-HDL and simulated using iSim. It is synthesized and demonstrated at ISE for xc5vlx330 in RPS3K board.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.107-119
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• 1988

An 8-channel digital filter bank with wave digital filters(WDF) is studied. Wave digital filtwr is automatically a directional filter. Using these properties, a new method for organizing the 8-channel digital filter bank is proposed. This will lead to enormous savings in memories for the digital signal processign chip.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1331-1333
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• 2001

In this study a measurement equipment was designed and made for the nonlinear dielectric constants in dielectrics. The determining method of the nonlinear dielectric constants also was proposed. The measurement equipment was consisted of the wave generation part, the high voltage amplifier part, the measurement part and the data acquisition part. In this equipment the measurement control and the data processing could be conducted by computer. In order to determine the nonlinear dielectric constants alternating sign-wave electric fields are applied to dielectrics with different magnitude and the waves of the electric fields and the response from dielectrics are stored in computer memories. The harmonics of dielectric displacement are obtained by the Fourier transformation of these waves. The nonlinear dielectric constants are determined at the relatively low-field region. The experiment for PZT ceramic samples was done by the equipment and the determining method and as the result meaningful data were obtained.