• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.13-17
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• 2006

Dense and periodic arrays of holes and tungsten none dots were fabricated on silicon oxide and silicon. The holes were approximately 25 nm wide, 40 nm deep, and 60 nm apart. To obtain nano-size patterns, self-assembling resists were used to produce layer of hexagonally ordered parallel cylinders of polymethylmethacrylate(PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS mask for pattern transfer. The silicon oxide was removed by fluorine-based reactive ion etching(RIE). Selectively deposited tungsten nano dots were formed inside nano-sized trench by using a low pressure chemical vapor deposition(LPCVD) method. Tungsten nano dot and trenched silicon sizes were 26 nm and 30 nm, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.19-27
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• 2003

Surface finishes of PCB laminates are important in the solder joint reliability of flip chip package because the types and thicknesses of intermetallic compound(IMC), and compositions and hardness of solders are affected by them. In this study, effects of surface finishes of PCB on the low cycle fatigue resistance of Sn-based lead-free solders; Sn-3.5Ag, Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag-XBi(X=2.5, 7.5) and Sn-0.7Cu were investigated for the Cu and Au/Ni surface finish treatments. Displacement controlled room temperature lap shear fatigue tests showed that fatigue resistance of Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag and Sn-0.7Cu alloys were more or less the same each other but much better than that of Bi containing alloys regardless of the surface finish layer used. In general, solder joints on the Au/Ni finish showed better fatigue resistance than those on the Cu finish. Cross-sectional fractography revealed microcracks nucleation inside of the interfacial IMC near the solder mask edge, more frequently on the Cu than the Au/Ni surface finish. Macro cracks followed the solder/IMC interface in the Bi containing alloys, while they propagated in the solder matrix in other alloys. It was ascribed to the Bi segregation at the solder/IMC interface and the solid solution hardening effect of Bi in the $\beta-Sn$ matrix.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.