• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.4
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• pp.1042-1058
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• 2024

Terahertz (THz) communication is becoming a key technology for future 6G wireless networks because of its ultra-wide band. However, the implementation of THz communication systems confronts formidable challenges, notably beam splitting effects and high computational complexity associated with them. Our primary objective is to design a hybrid precoder that minimizes the Euclidean distance from the fully digital precoder. The analog precoding part adopts the delay-phase alternating minimization (DP-AltMin) algorithm, which divides the analog precoder into phase shifters and time delayers. This effectively addresses the beam splitting effects within THz communication by incorporating time delays. The traditional digital precoding solution, however, needs matrix inversion in THz massive multiple-input multiple-output (MIMO) communication systems, resulting in significant computational complexity and complicating the design of the analog precoder. To address this issue, we exploit the characteristics of THz massive MIMO communication systems and construct the digital precoder as a product of scale factors and semi-unitary matrices. We utilize Schatten norm and Hölder's inequality to create semi-unitary matrices after initializing the scale factors depending on the power allocation. Finally, the analog precoder and digital precoder are alternately optimized to obtain the ultimate hybrid precoding scheme. Extensive numerical simulations have demonstrated that our proposed algorithm outperforms existing methods in mitigating the beam splitting issue, improving system performance, and exhibiting lower complexity. Furthermore, our approach exhibits a more favorable alignment with practical application requirements, underlying its practicality and efficiency.

• ETRI Journal
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• v.27 no.5
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• pp.639-642
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• 2005

This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.6
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• pp.2908-2924
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• 2019

Multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) is widely applied in wireless communication by virtue of its excellent properties in data transmission rate and transmission accuracy. However, as a major drawback of MIMO-OFDM systems, the high peak-to-average power ratio (PAPR) complicates the design of the power amplifier at the receiver end. Some available PAPR reduction methods such as selective mapping (SLM) suffer from high computational complexity. In this paper, a low-complexity SLM method based on active constellation extension (ACE) and joint space-time selective mapping (AST-SLM) for reducing PAPR in Alamouti STBC MIMO-OFDM systems is proposed. In SLM scheme, two IFFT operations are required for obtaining each transmission sequence pair, and the selected phase vector is transmitted as side information(SI). However, in the proposed AST-SLM method, only a few IFFT operations are required for generating all the transmission sequence pairs. The complexity of AST-SLM is at least 86% less than SLM. In addition, the SI needed in AST-SLM is at least 92.1% less than SLM by using the presented blind detection scheme to estimate SI. We show, analytically and with simulations, that AST-SLM can achieve significant performance of PAPR reduction and close performance of bit error rate (BER) compared to SLM scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.4
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• pp.1330-1350
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• 2022

As a preprocessing operation of transmitter antennas, the hybrid precoding is restricted by the limited computing resources of the transmitter. Therefore, this paper proposes a novel hybrid precoding that guarantees the communication efficiency with low complexity and a fast computational speed. First, the analog and digital precoding matrix is derived from the maximum eigenvectors of the channel matrix in the sub-connected architecture to maximize the communication rate. Second, the extended power iteration (EPI) is utilized to obtain the maximum eigenvalues and their eigenvectors of the channel matrix, which reduces the computational complexity caused by the singular value decomposition (SVD). Third, the Aitken acceleration method is utilized to further improve the convergence rate of the EPI algorithm. Finally, the hybrid precoding based on the EPI method and the Aitken acceleration algorithm is evaluated in millimeter-wave (mmWave) massive multiple-input and multiple-output (MIMO) systems. The experimental results show that the proposed method can reduce the computational complexity with the high performance in mmWave massive MIMO systems. The method has the wide application prospect in future wireless communication systems.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.71-76
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• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.3
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• pp.59-64
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• 2023

Fire and disaster broadcasting systems are divided into analog, digital, and network-based digital public address systems, and important specifications in network-based digital public address systems are low-latency audio, high sampling rate, and multi-channel input and output. In the past, it has been widely used to the AoE method for distinguishing based on the MAC address of the data link layer. However, this method has a problem of increasing complexity and cost. This proposal is an AoIP/UDP method, which allows communication to be easily distinguished by IP address without the need for a separate redundant network, so that the network can be freely used and configured, and cost can be reduced by reducing complexity. After implementing the AoIP/UDP method, the experimental results showed that the cost was improved with the equivalent performance with 2.66ms latency.

• ETRI Journal
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• v.26 no.2
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• pp.92-100
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• 2004

In this paper, we propose an efficient method to broadcast digital television signals using single frequency networks (SFNs) within the Advanced Television Systems Committee (ATSC) transmission systems. In implementing the SFNs of an 8-vestigial side band (8-VSB) Digital Television (DTV) system, the ambiguity problem of the trellis coder is unavoidable in a conventional ATSC transmission system. We propose a memory initialization of the trellis coder to resolve this ambiguity problem. Since the proposed scheme to synchronize multiple transmitters minimizes the changes from the conventional ATSC system, the hardware complexity for these changes is very low. Our simulation results show that the proposed scheme makes a less than 0.1 dB degradation at the threshold of visibility with a bit error rate of $3{\times}10^{-6}$ in the additive white Gaussian noise (AWGN) channel. It is possible to reduce the performance degradation by increasing the initialization period of the proposed scheme.

• Agribusiness and Information Management
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• v.5 no.1
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• pp.31-41
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• 2013

The research assesses the impact of a digital procurement (e-purjee) system for sugarcane growers in Bangladesh. The system itself is simple, transmitting purchase orders to local farmers via SMS text notification. It replaces a traditional paper-based system fraught with low reliability and delivery delays. Applying expected value theory, and using decision tree representations to depict growers' decision-making complexity in an information-asymmetric environment, we compute outcomes for the strategies and sub-strategies of ICT vs. traditional paper-based order management from the sugarcane growers' perspective. The study results show that the digital procurement system outperforms the paper-based system by tangibly reducing growers' economic losses. The digital system also appears to benefit growers non-monetarily, because of reduced uncertainty and a higher level of perceived fairness. Sugarcane growers appear to value the non-monetary benefits even higher than the economic advantages of the e-purjee system.

• ETRI Journal
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• v.34 no.2
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...