• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2008년도 추계 학술발표회
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• pp.549-558
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• 2008

Well known and widely used in urban area and limited installation condition, a low noise and vibration piling method which has being called Bored Prefabricated Piling Method was reviewed in terms of design guide, and introduced a few case as well. Among the areas being applied of that method, a structural guide of architectural foundation was reviewed and compared to civil engineering foundation area to provide wider information for the foundation engineers. With introducing a few case application including pile load testing review especially dynamic testing in normal building foundation work, engineers may have a useful information on the design and construction of the piling method even different engineering area. It may also make enhancement a view of foundation engineering knowledge to various pile foundation area.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

• International Journal of Fluid Machinery and Systems
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• 제7권2호
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• pp.68-79
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• 2014

The type of turbine developed is based on the very low head of water potential source for the electric power production. The area of research is focused for the axial water turbine that can be applied at the simple site open channel with has a very low cost and environmental impact compared to the conventional hydro installation. High efficiency of axial turbine which applied to the very low potential head will made this type of turbine can be used at wider potential site. Existing irrigation weir and river area will be the perfect site for this turbine. This paper will compare the effects of the variation of swirl velocity criterion during the design of the blade of guide vane and rotor of the turbine. Effects of the swirl velocity criterion is wider known as a vortex conditions (free vortex, force vortex and swirl velocity constant), and the free vortex is the very popular condition that applied by most of turbine designer, therefore will be interesting to do a comparison against other criterion. ANSYS Fluent will be used for simulation and to determine the predictive performance obtained by each of design criteria.

• 대한전기학회논문지:전력기술부문A
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• 제49권5호
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• pp.226-232
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• 2000

This paper presents application results of the augmented matrix eigen-sensitivity theories to TCSC siting problem for damping the inter-area low frequency oscillation in the large KEPCO system. First and second-order eigen-sensitivities of the inter-area low frequency oscillation in the large KEPCO system. First and second-order eigen-sensitivities of the inter-area mode are computed fro changes in susceptance of the transmission lines. The lines having high sensitivity are chosen as the initial candidates for installing TCSC. Then for each of the chosen candidates, Bodeplot of the transfer function with line susceptance as the input and the bus voltage at one side of the line as the output is computed. Using the Bode plots, the lines having any zeros near the inter-area mode are screened out since design of TCSC controller is very difficult in such a case. The $H_{\infty}$ TCSC controller installed at any finally chosen candidate is found to be effective in damping the inter-area oscillation, and the proposed TCSC siting algorithm is proved to be valid. Design of $H_{\infty}$ controller is described in Part IIof this paper.

• 교육녹색환경연구
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• 제9권2호
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• pp.30-37
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• 2010

This study purposed realization and a phase reduction of school building $CO_2$ emissions. Accordingly selected standard school buildings and evaluated life cycle environmental load($CO_2$). This study proposed Green building technology which separated design sector, energy sector, afforestation sector for carbon-neutral city school buildings realization of M-city. As a result, elementary, middle and high schools of M-city built in the year 2013 were required that design sector was Energy Performance Index(EPI) 75 point and energy sector was solar installations more than 25% of the power usage, Solar systems installed more than 10% of total gas consumption and the area of afforesting more than 35% of the ecological area to achieve 30% $CO_2$ reduction compared to the Respectively standard school buildings.

• 전기전자학회논문지
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• 제18권2호
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• pp.198-205
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• 2014

정보화 기술의 발전에 따라 웨어러블 장치, 휴대용 장치, RFID와 같은 소형 애플리케이션에 대한 관심이 증가하고 있고, 여기에 적용하기 위한 소형 암호화 회로의 중요성이 강조되고 있다. 본 논문에서는 소형 애플리케이션에 적합한 AES 기반 암호화 회로를 제안한다. 제안하는 회로에서는 저장 공간의 최소화, 연산 자원의 공유를 통해서 크기를 최소화 하였다. 제안하는 회로는 $8{\times}16$ 비트 크기의 SRAM 두 개를 사용하였으며, 65nm 표준 셀 라이브러리를 이용하여 합성한 결과 2,241 개의 게이트로 구현되었고, 처리 속도는 초당 50.57M 비트이다. 따라서 저면적 암호화 회로를 필요로 하는 다양한 애플리케이션에 적용하여 사용할 수 있다.

• 한국통신학회논문지
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• 제25권8B호
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• pp.1477-1486
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• 2000

본 논문에서는 조합 논리 회로의 면적과 전력 소모를 낮추기 위한 효율적인 커널 기반의 분할 알고리듬을 제안 한다. 제안한 알고리듬은 커널을 이용하여 회로를 분할함으로써 회로의 전력 소모를 줄이고 분할된 회로들의 중복 되는 게이트를 최소화시켜 면적 overhead를 감소시킨다. MCNC 표준 테스트 회로에 대한 실험을 통하여 제안된 알고리듬이 면적과 전력소모면에 있어서 기존의 precomputation 회로 구조에 바탕을 둔 알고리듬에 비해 전력 소모는 평균 43.6% 면적은 평균30.7% 향상된 결과를 보인다.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2005년도 지반공학 공동 학술발표회
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• pp.443-452
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• 2005

The compaction pile methods with low replacement area ratio used sand(SCP) or gravel(GCP) has been usually applied to improvement of soft clay deposits. In order to design accurately compaction pile method with low replacement area ratio, it is important to understand the mechanical interaction between sand piles and clays and its mechanism during consolidation process of the composition ground. In this paper, a series of numerical analyses on composition ground improved by SCP and GCP with low replacement area ratio were carried out, in order to investigate the mechanical interaction between sand piles and clays. The applicability of numerical analyses, in which and elasto-viscoplastic consolidation finite element method was applied, could be confirmed comparing with results of a series of model tests on consolidation behaviors of composition ground improved by SCP. And,through the results of the numerical analyses, each mechanical behaviors of compaction piles and clays in the composition ground during consolidation was elucidated, together with stress sharing mechanism between compaction piles and clays.

• 한국정보통신학회논문지
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• 제13권12호
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• pp.2633-2640
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• 2009

본 논문에서는 터치스크린 컨트롤러용 IC를 위한 저면적, 저전력, 고속 EEPROM 회로 설계기술을 제안하였다. 저면적 EEPROM 기술로는 SSTC (Side-wall Selective Transistor Cell) 셀을 제안하였고 EEPROM 코어회로에서 반복되는고전압 스위칭 회로를 최적화하였다. 저전력 기술은 디지털 Data Bus 감지 증폭기 회로를 제안하였다. 그리고 고속 EEPROM 기술로는 Distributed DB 방식이 적용되었으며, Dual Power Supply를 사용하여 EEPROM 셀과 고전압 스위칭 회로의 구동전압은 로직전압 VDD(=1.8V)보다 높은 전압인 VDDP(=3.3V)를 사용하였다. 설계된 128Kb EEPROMIP(Intellectual Property)의 레이아웃 면적은 $662.31{\mu}m{\times}1314.89{\mu}m$이다.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.