• 제목/요약/키워드: low jitter

검색결과 157건 처리시간 0.031초

주파수 동기를 위한 저 잡음 2.5V 300Mhz CMOS PLL (A Low-Jitter 2.5V 300MHZ CMOS PLL for Frequency Synthesizer)

  • 권진규;이종화;조상복
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1189-1192
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    • 2003
  • 본 논문에서는 노이즈를 고려한 PLL를 설계하였다. 30Mhz∼300Mhz으로 동작하는 VCO를 설계하였다. VCO를 평균 250Mhz으로 동작하도록 하고 reference 주파수, 62.5Mhz로 locking하는 PLL를 설계를 하였다. 300Mhz PLL의 기본적인 구조로 PLL은 PFD(Phase frequency detector), CP(Charge Pump), LF(Loop filter), VCO(Voltage controlled Oscillator)와 Divider로 구성되었다. PFD과 CP는 Dead Zone를 줄이고, 큰 gm를 가지도록 설계를 하였다. PLL에서 가장 중요한 블락인, VCO는 One Chip으로 설계하기 위해 Ring Oscillator로 설계를 하였다. 2.5V 62.5MHZ의 외부 신호를 300MHZ을 발진하는 VCO에서 분주하여 clock synthesizer를 설계하였다. 본 논문은 Hynix0.25공정을 사용하여 설계를 하였으며, 2.5V의 공급 전원을 사용하였다.

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네트워크 기반 임베디드 시스템을 위한 IEEE1588 시간동기 구현 (Implementing IEEE1588 based Clock Synchronization for Networked Embedded System)

  • 전종목;김동길;김은로;이동익
    • 대한임베디드공학회논문지
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    • 제9권1호
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    • pp.33-41
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    • 2014
  • This paper presents a IEEE1588 based clock synchronization technique for a sRIO (Serial RapidIO) network which is applied to a submarine system. Clock synchronization plays a key role in the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipset has been widely used for the synchronization of various industrial applications. However, there is no chipset available for the sRIO network that can offer many advantages, such as low latency and jitter. In this paper, the IEEE1588 algorithm for a sRIO network is implemented using only software without any dedicated chipset. The proposed approach is verified with experimental setup.

New Material for a Super Resolution Disc

  • Kwak, Keum-Cheol;Kim, Sun-Hee;Lee, Chang-Ho;Song, Ki-Chang
    • 정보저장시스템학회논문집
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    • 제3권2호
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    • pp.54-58
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    • 2007
  • Using metal/Si materials as a recording layer, we have achieved good results for a SR disc (super resolution disc). Mainly by controlling metal composition and the ratio of metal to Si of recording layer, signal qualities were greatly enhanced. At the mark length of 75nm, the best CNR (Carrier to Noise Ratio) was about 45dB. Write power was reduced down to about 6.5mW. LFN (Low Frequency Noise) could also be reduced down to 14dB. Single tone pattern jitters for every mark whose length is from 2T through 8T were achieved to be below 10%. The readout signal was stable sustaining CNR>40dB during about 15,000 times reading. The so-called "3T-problem" could be avoided.

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Jitter Correction of the Face Motion Capture Data for 3D Animation

  • Lee, Junsang;Han, Soowhan;Lee, Imgeun
    • 한국컴퓨터정보학회논문지
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    • 제20권9호
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    • pp.39-45
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    • 2015
  • Along with the advance of digital technology, various methods are adopted for capturing the 3D animating data. Especially, in 3D animation production market, the motion capture system is widely used to make films, games, and animation contents. The technique quickly tracks the movements of the actor and translate the data to use as animating character's motion. Thus the animation characters are able to mimic the natural motion and gesture, even face expression. However, the conventional motion capture system needs tricky conditions, such as space, light, number of camera etc. Furthermore the data acquired from the motion capture system is frequently corrupted by noise, drift and surrounding environment. In this paper, we introduce the post production techniques to stabilizing the jitters of motion capture data from the low cost handy system based on Kinect.

AC PDP에서 고속 어드레싱을 위한 ADR(Address During Reset) 구동 방식 (The ADR(Address During Reset) Driving Method for High-Speed Addressing in an AC-PDP)

  • 송근영;김근수;이석현
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제54권6호
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    • pp.269-273
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    • 2005
  • In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be implemented by reducing the address discharge time lag through the priming effect. This paper suggests a new ADR(Address During Reset) driving method which provides priming particles by a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately 100ns reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction of about 29$\%$ in linht emitted during the reset period considerably.

새로운 구동방식을 이용한 어드레스 방전 지연시간의 감소 (The Reduction of Address Discharge Delay Time Using a New Driving Method)

  • 송근영;김근수;서정현;이석현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.123-125
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    • 2004
  • In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be achieved by reducing the address discharge delay time through the priming effect. This paper suggests a new ADR (Address During Reset) driving method which provides priming particles by using a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately loons reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction in light emitted during reset of about 29% which improved the dark contrast ratio considerably.

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사이라트론 구동용 제어회로 설계에 관한 연구 (Analysis and Design of The Thyratron Controller)

  • 김한기;정태원;차병헌
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 추계학술대회 논문집 학회본부 B
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    • pp.348-351
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    • 2000
  • There have been significant advances in thyratron performance in recent years. these advanced waveforms have increased the complexity and cost of drive circuits. Thyratrons can reliably switch anode voltages up to 40kV and conduct peak currents up to 10kA or more. So stable thyratron drivers are essential for reliable high voltage pulse modulators. In order to operate thyratron well, thyratron driver need high repetition rate, fast rising time and low jitter. In this paper, used power MOSFET/transformer combinations. Designed thyratron driver is satisfied requirements and experimental results are presented to confirm.

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AC PDP의 효율 향상을 위한 비대칭형 금속전극구조 (Improvement of Luminous Efficacy in AC PDP with Asymmetric Metal Electrode Structure)

  • 동은주;옥정우;윤초롬;이해준;이호준;박정후
    • 전기학회논문지
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    • 제57권4호
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    • pp.660-667
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    • 2008
  • To improve the luminous efficacy of PDPs, an AC PDP with new metal electrode structure is suggested. Operating voltage margin, power consumption, luminance, luminous efficacy, addressing jitter and ICCD image of test panel with proposed structure are measured, to compared with performances of the conventional ITO structure and proposed structures. To enhance luminous efficacy, we designed new structure which have asymmetric metal electrode structure. The experimental results show that the suggested structure shows luminance to maximum 89% and luminous efficacy to maximum 107% compared with conventional ITO standard structure. In addition, proposed structures with asymmetric electrode show low power consumption by $2{\sim}3%$, high luminance by $5{\sim}7%$, and high luminous efficacy by $2{\sim}3%$ compared with proposed symmetric electrode structures.

실시간 EtherCAT 마스터 구현에 관한 연구 (A Study on Implementation of Real-time EtherCAT Master)

  • 강성진
    • 반도체디스플레이기술학회지
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    • 제20권2호
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    • pp.131-136
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    • 2021
  • EtherCAT is an Ethernet-based fieldbus system standardized in IEC 61158 and SEMI, and widely used in the fields of factory automation, semiconductor equipment and robotics. In this paper, a real-time EtherCAT master is implemented on Linux operating systems and its performances are evaluated. To enhance the real-time capability of mainline Linux kernel, Xenomai is applied as a real-time framework and an open source EtherCAT master stack, Simple Open EtherCAT Master (SOEM), is installed on it. Unlike other studies, the real-time performance of the EtherCAT master is evaluated at the output of the network interface card, so that the evaluation results include all possible effects from the EtherCAT master system. The implemented EtherCAT master can send and receive packets up to 20KHz control frequency with low jitter, even in stressed condition.

오픈소스 기반의 실시간 EtherCAT 제어 시스템의 구현 (Implementation of Real-time EtherCAT Control System based on Open Source)

  • 경윤진;최동일
    • 로봇학회논문지
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    • 제18권3호
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    • pp.281-284
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    • 2023
  • Real-time control communication network system is important for developing defense robots because it affects environmental interaction, performance, and safety. We propose a real-time control communication network using the Xenomai real-time operating system and the open-source EtherCAT master library, SOEM. EtherCAT is an Ethernet-based industrial communication method. It has low latency and many functions such as cable redundancy and distributed clock synchronization. We use Xenomai RTOS and Intel NUC to develop the system. Experimental tests demonstrate the Real-time EtherCAT master implementation, and communication with CiA301-based slave devices. The jitter measurement was conducted to validate the real-time performance of the system. The proposed system shows possibility for real-time robotics applications in various defense robots.