• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.1
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• pp.11-21
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• 2008

In conventional video coding, the complexity of encoder is much higher than that of decoder. However, as more needs arises for extremely simple encoder in environments having constrained energy such as sensor network, much investigation has been carried out for eliminating motion prediction/compensation claiming most complexity and energy in encoder. The Wyner-Ziv coding, one of the representative schemes for the problem, reconstructs video at decoder by correcting noise on side information using channel coding technique such as turbo code. Since the encoder generates only parity bits without performing any type of processes extracting correlation information between frames, it has an extremely simple structure. However, turbo decoding errors occur in noisy side information. When there are high-motion or occlusion between frames, more turbo decoding errors appear in reconstructed frame and look like Salt & Pepper noise. This severely deteriorates subjective video quality even though such noise rarely occurs. In this paper, we propose a computationally extremely light encoder based on symbol-level Wyner-Ziv coding technique and a new corresponding decoder which, based on a decision whether a pixel has error or not, applies median filter selectively in order to minimize loss of texture detail from filtering. The proposed method claims extremely low encoder complexity and shows improvements both in subjective quality and PSNR. Our experiments have verified average PSNR gain of up to 0.8dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.965-972
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• 2005

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen for second generation digital video broadcasting standard, are required a large number of computation due to large size of coded block and iteration. Therefore, we presented two kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algerian. Secondly, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and computational complexity of early detected method is about $50\%$ offs in case of check node update, $99\%$ offs in case of check node update compared to conventional scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.21-27
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• 2013

In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.24-31
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• 2010

A receiver architecture with low complexity for chirp spread spectrum (CSS) of IEEE 802.15.4a is proposed. To demodulate the received signal at the highest signal to noise power ratio, matched filter is generally adopted for the receiver of wireless communication systems. It is, however, not resonable to adjust the matched filter to the receiver of CSS whose objectives are low complexity, low cost and low power consumption since complexity of the matched filter is high. In this paper, we propose a new receiver architecture using differential multiplication and accumulator not matched filter for demodulation. Also, bi-orthogonal decoder implemented by only adder/subtractor is proposed. The hardware resources for implementation are reduced in the proposed receiver architecture, although bit error rate performance is low compared with the receiver architecture based on the matched filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1123-1126
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• 1999

In this paper, we propose a real-time implementation of the MPEG-1 layer III and MPEG-2 layer III LSF audio decoding system based on OAK DSP Core. In order to solve the problem of resolution, the system has been used floating-point operation and double precision in dequantization module. The size of ROM is reduced by using the Run-length algorithm of reordered index. The subband synthesis filter module is optimized to have low computational complexity in terms of the size of ROM or RAM. To construct a efficient system, we used both the DSP Core and Parser-Huffman decoder which is implemented with VHDL.