• 대한원격탐사학회지
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• 제26권2호
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• pp.239-249
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• 2010

세계 최초로 정지궤도에 위치한 해색 위성의 위성자료를 처리/분석하는 시스템인 해양자료처리 시스템(GDPS)의 개발은 정지궤도 해색탑재체(GOCI)의 하드웨어 개발과 동시에 시작되었다. GOCI의 관측 영역에 특화된 대기 알고리즘 및 해양 분석 알고리즘을 개발하고 소프트웨어 모듈화 하여, GOCI가 수신한 총 복사휘도 정보인 레벨 1B 자료에서 레벨 2와 3의 해양 분석 자료를 생성할 수 있는 기능을 개발하였다. 해양자료처리시스템은 해양위성센터에서 표준 운영시스템으로 활용될 뿐만 아니라, 일반 사용자에게 기본 GOCI 자료처리시스템으로 활용될 수 있도록 다양한 버전으로 개발되었다. 부가적인 기능으로 GOCI 이미지 위성 배포파일(LRIT) 생성, 복사보정계수 계산, 영역 분할/병합, 시계열 분석 등을 제공한다. 개발된 GDPS 시스템은 30분 이내에 자료를 안정적으로 생산하여, 이용자 요구사양을 만족시켰다. 해양자료처리 시스템은 여러 해양환경분석 알고리즘을 통해 해양의 장단기 환경특성 변화를 감시하는데 훌륭한 역할을 할 수 있을 것으로 기대된다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 대한원격탐사학회지
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• 제36권6_1호
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• pp.1449-1463
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• 2020

최근 지구온난화에 따른 기후변화 문제의 심각성이 커지면서 국가 온실가스 배출량을 상쇄시킬 수 있는 산림의 탄소흡수에 대한 중요성이 높아지고 있으며, 기후변화협약에 따라 국가의 산림 탄소흡수량을 국지적인 수준에서 과학적이고 정밀하게 산출할 것이 요구되고 있다. 본 연구에서는 위성영상과 일기상 자료를 함께 활용함으로써 산림 광합성의 민감한 일변화를 반영하고, 안정된 산림으로서 대표성을 가지는 광릉숲(Gwangneung Forest) 극상림(climax forest)의 플럭스관측 자료를 참조하여 GPP(gross primary production) 재현 모델을 수립하고, 수종 및 임령에 따른 탄소흡수량 조견표를 적용하여, 우리나라의 국지지역에 최적화된 Tier 2.5 수준의 일일 탄소흡수능 격자자료를 산출하였다. 2013년 1월 1일부터 2015년 12월 31일까지 1,095일간의 실험에서, 일일 기준탄소흡수능(reference amount of CO2 absorption, RACA) 산출 모델은 상관계수 0.948의 높은 정확도를 나타냈으므로, 향후 Tier 3 수준의 일일 실제탄소흡수능(actual amount of CO2 absorption, AACA)을 정확히 산출하기 위해서는 장기간의 상세산림조사 자료와의 결합이 필요할 것이다.