• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.1-10
• /
• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.4
• /
• pp.91-98
• /
• 1992

In this paper, a new heuristic algorithm for designing combinational circuits suitable for verification testing is presented. The design method consists of argument reduction, input partitioning, output partitioning, and logic minimization. A new heuristic algorithm for input partitioning and output partitioning is developed and applied to designing combinational circuits to demonstrate its effectiveness.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.2
• /
• pp.338-346
• /
• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.823-826
• /
• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.43 no.6 s.312
• /
• pp.40-47
• /
• 2006

This paper introduces an efficient CRC logic partitioning algorithm to design pipelined parallel CRC circuits aimed at improving speed performance. Focusing on the cases that the input data width is greater than the polynomial degree, equations are derived to divide the parallel CRC logic and decide the length of the pipeline stage. Through design experiments on different types of parallel CRC circuits, we have found a significant reduction in delay by adopting our approach.

• Journal of the Korea Society for Simulation
• /
• v.5 no.2
• /
• pp.73-84
• /
• 1996

As circuits are larger and more complicated, logic simulation is playing a very important role in design verification. A good simulator should be fast and accurate, but unknown values in 3 value simulator may generate X-propagation problem which makes inaccurate output values. In this paper, a new partitioning method is devised to deal with X-propagation problem efficiently and an efficient algorithm is developed which is able to optimize time and accuracy by controlling partition depths. The results prove the effectiveness of the new simulation algorithm using some benchmark circuits.

• Proceedings of the KIEE Conference
• /
• 1996.11a
• /
• pp.291-293
• /
• 1996

Logic simulation is playing a very important role for design verification as circuits are larger and more complicated. However unknown values in 3 value simulators may generate the X-propagation problem which makes inaccurate output values. In this paper, a new partitioning method and a new simulation algorithm are developed to deal with the X-propagation problem efficiently. The new algorithm can optimize simulation time and accuracy by controlling partition depth. Benchmark results prove the effectiveness of the new simulation algorithm.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.789-792
• /
• 2005

In this paper, we propose a method that applies pipeline architecture to parallel CRC circuits. We developed a logic partitioning algorithm for applying pipeline architecture. Our algorithm can be used for the polynomial and the input data width, both of arbitrary length and minimize the logic level. Design experiments show the superiority of our approach in reducing the delay in comparison with previous works.

• ETRI Journal
• /
• v.24 no.6
• /
• pp.473-476
• /
• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.8B
• /
• pp.1477-1486
• /
• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.