• Speech Sciences
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• v.11 no.2
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• pp.181-192
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• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• Speech Sciences
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• v.11 no.3
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• pp.143-156
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• 2004

In this paper, we implemented a vocabulary-independent speech recognizer using the TMS320VC33 DSP. For this implementation, we had developed very small-sized recognition engine based on diphone sub-word unit, which is especially suited for embedded applications where the system resources are severely limited. The recognition accuracy of the developed recognizer with 1 mixture per state and 4 states per diphone is 94.5% when tested on frequently-used 2000 words set. The design of the hardware was focused on minimal use of parts, which results in reduced material cost. The finally developed hardware only includes a DSP, 512 Kword flash ROM and a voice codec. In porting the recognition engine to the DSP, we introduced several methods of using data and program memory efficiently and developed the versatile software protocol for host interface. Finally, we also made an evaluation board for testing the developed hardware recognition module.

• Journal of Information Processing Systems
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• v.17 no.2
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• pp.227-241
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• 2021

Object detection techniques based on deep learning such as YOLO have high detection performance and precision in a single channel video stream. In order to expand to multiple channel object detection in real-time, however, high-performance hardware is required. In this paper, we propose a novel back-end server framework, a real-time AI vision platform (RAVIP), which can extend the object detection function from single channel to simultaneous multi-channels, which can work well even in low-end server hardware. RAVIP assembles appropriate component modules from the RODEM (real-time object detection module) Base to create per-channel instances for each channel, enabling efficient parallelization of object detection instances on limited hardware resources through continuous monitoring with respect to resource utilization. Through practical experiments, RAVIP shows that it is possible to optimize CPU, GPU, and memory utilization while performing object detection service in a multi-channel situation. In addition, it has been proven that RAVIP can provide object detection services with 25 FPS for all 16 channels at the same time.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of Korea Multimedia Society
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• v.13 no.10
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• pp.1423-1435
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• 2010

Building wireless sensor networks requires a constituting sensor node to consider the following limited hardware resources: a small battery lifetime limiting available power supply for the sensor node, a low-power microprocessor with a low-performance computing capability, and scarce memory resources. Despite such limited hardware resources of the sensor node, the sensor node platform needs to activate real-time sensing, guarantee the real-time processing of sensing data, and exchange data between individual sensor nodes concurrently. Therefore, in this paper, we propose an energy-efficient real-time task scheduling technique for battery-powered wireless sensor nodes. The proposed energy-efficient task scheduling technique controls the microprocessor's operating frequency and reduces the power consumption of a task by exploiting the slack time of the task when the actual execution time of the task can be less than its worst case execution time. The outcomes from experiments showed that the proposed scheduling technique yielded efficient performance in terms of guaranteeing the completion of real-time tasks within their deadlines and aiming to provide low power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1079-1085
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• 2013

Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple $2^M$ decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.91-97
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• 2017

IoT (Internet of Things) systems are based on heterogeneous hardware systems of different types of devices interconnected each other, ranging from miniaturized and low-power wireless sensor node to cloud servers. These IoT systems composed of heterogeneous hardware utilize data sets collected from a particular set of sensors or control designated actuators when needed using open APIs created through abstraction of devices' resources associated to service applications. However, previously existing IoT services have been usually developed based on vertical platforms, whose sharing and exchange of data is limited within each industry domain, for example, healthcare. Such problem is called 'data silo', and considered one of crucial issues to be solved for the success of establishing IoT ecosystems. Also, IoT services may need to dynamically organize their services according to the change of status of connected devices due to their mobility and dynamic network connectivity. We propose a way of dynamically composing IoT services under the concept of WoT (Web of Things) where heterogeneous devices across different industries are fully integrated into the Web. Our approach allows developers to create IoT services or mash them up in an efficient way using Web objects registered into multiple standardized horizontal IoT platforms where their resources are discoverable and accessible. A Web-based service composition tool is developed to evaluate the practical feasibility of our approach under real-world service development.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.75-81
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• 2014

The integral image is the sum of input image pixel values. It is mainly used to speed up processing of a box filter operation, such as Haar-like features. However, large memory for integral image data can be an obstacle on an embedded hardware environment with limited memory resources. Therefore, an efficient method to store the integral image is necessary. In this paper, we propose a memory size reduction hardware design for integral image. The hardware design is used two methods. It is the new integral image memory and modulo calculation for reducing integral image data. The new integral image memory has additional calculation overhead, but it is not obstacle in hardware environment that parallel processing is possible. In the Xilinx Virtex5-LX330T targeted experimental result, integral image memory can be reduced by 50% on a $640{\times}480$ 8-bit gray-scale input image.

• Korean Journal of Cognitive Science
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• v.24 no.2
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• pp.95-109
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• 2013

With the rapid evolution of the personal device environment, the demand for natural language applications is increasing. This paper proposes a morpheme segmentation and part-of-speech tagging model, which provides the first step module of natural language processing for many languages; the model is designed for mobile devices with limited hardware resources. To reduce the number of morpheme candidates in morphological analysis, the proposed model uses a method that adds highly possible morpheme candidates to the original outputs of a conventional left-longest-match-preference method. To reduce the computational cost and memory usage, the proposed model uses a method that simplifies the process of calculating the observation probability of a word consisting of one or more morphemes in a conventional hidden Markov model.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.7
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• pp.1-6
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• 2008

In industrial fields, human works are being replaced by robots. However, as the use of robots is limited in the process industry where they are operated fixedly, humanoid robots with wide applications need to be developed. Currently a great deal of research is being conducted on humanoid robots with the object of replacing humans in the workplace. However, because of the lack of relevant hardware and difficulty in mechanical parts, only very simple and limited progress is being made. In an effort to overcome these limitations, the purpose of the present study is to develop a kinematical mechanism and a controller. To this end, master arms with 3 degrees-of-freedom for the shoulders and the arms were composed which were able to reproduce human-like motions by simulating the characteristics of joint variables and the trajectory of the end-effector.