• Journal of the Korea Society for Simulation
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• v.32 no.3
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• pp.93-108
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• 2023

In manufacturing productivity analysis, understanding the intricate interplay among factors like facility performance, layout design, and workforce allocation within the production line is imperative. This paper introduces a simulation-based methodology tailored to food manufacturing, progressively expanding scenarios to analyze production enhancement. The target system is a food processing plant, encompassing production processes, including warehousing, processing, subdivision, packaging, inspection, loading, and storage. First, we analyze the target system and design a simulation model according to the actual layout arrangement of equipment and workers. Then, we validate the developed model reflecting the real data obtained from the target system, such as the workers' working time and the equipment's processing time. The proposed model aims to identify optimal factor values for productivity gains through incremental scenario comparisons. To this end, three stages of simulation experiments were conducted by extending the equipment and worker models of the subdivision and packaging processes. The simulation experiments have shown that productivity depends on the placement of skilled workers and the performance of the packaging machine. The proposed method in this study will offer combinations of factors for the specific production requirements and support optimal decision-making in the real-world field.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.