• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.318-321
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• 2002

This paper presents a proper condition to achieve high conversion efficiency using PC1D simulator on sri-crystalline Si solar cells. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 $\mu\textrm{m}$, front surface recombination velocity 100 cm/s, sheet resistivity of emitter layer 100 Ω/$\square$, BSF thickness 5 $\mu\textrm{m}$, doping concentration 5${\times}$10$\^$19/ cm$\^$-3/. Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.63-67
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• 1992

Shallow $p^{+}-n,n^{+}-p$ diodes have been fabricated using rapid thermal diffusion by solid diffusion source and rapid thermal alloying with pure Aluminum. Diode area and junction depth are designed about 2.83$[\times}10^{-3}cm^{2}$ and 250nm, respectively. Electrical characteristics of $p^{+}-n$ diode show that the ideality factor is 1.04 and reverse current density is 29.3nA/$cm^{2}$, respectively. On the other hand, those of $n^{+}-p$ diode show that the ideality factor is 1.05 and reverse current density is 85.2pA/$cm^{2}$. The reverse currents are measured at 5V reverse bias after rapid thermal alloying for all the measurement.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.111-118
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• 1995

The three-dimentional effects on the breakdown voltage of non-reachthrough planar junctions which have the finite lateral radius of window curvature are analytically investigated. The critical electric fields at breakdown and the breakdown voltages are expressed successfully in a form which is normalized to the parallel plane case. The analytical results are in excellent agreement with the published results of experiment and the quasi-three-dimensional device simulation by MEDICI for non-reachthrough plane junctions having different background doping and junction depth. The results may be applicable to the estimations of breakdown voltages in many practical power devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.79-82
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• 1995

The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.136-143
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• 1996

A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.205-209
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• 1991

The conventional modeling equations for planar MOSFET can not be directly used for zero or minus junction depth concave MOSFET. In this paper, we suggest a new model which can simulate the electrical characteristics of concave MOSFET. The threshold voltage modeling was achieved using the charge sharing method considering the relative difference of source and drain depletion widths. To analyze the ID-VDS characteristics, the conventional expressions for planar MOSFET were employed with the electrical channel length as an effective channel length and the channel length modulation factor as ${\alpha}$ΔL. By comparing the proposed model with experimental results, we could get reasonably similar curves and we proposed a concave MOSFET conditiion which shows no short channel effect of threshold voltage(V${\gamma}$).

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1991-1993
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• 2002

This paper presents the PDMS surface characteristic change after the plasma process and the electroosmotic flow control technique for the two-dimensional focusing in the micro channels made of PDMS and glass. The channels are fabricated by plastic molding and micromachining technique. To observe the surface characteristic change as time elapses, we measure the contact angle of water on the surface and the velocity of the electroosmotic flow in a channel. The electric field adequate for focusing of a core flow in a confluence channel is obtained by the experiment. The computer simulation is performed to obtain the width and the depth of the core flow for several junction angles of the confluence channel.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.393-393
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• 2011

오늘 날 태양전지 산업에서 가장 많은 생산을 하고 있는 분야는 결정질 태양전지분야이다. 현재는 이러한 시대적 요구에 따라 많은 연구가 진행되고 있는데 특히 junction을 이루는 n layer의 doping profile을 선택적으로 형성하여 개방전압 및 단락전류를 향상시키는 연구가 활발히 진행되고 있다. 본 연구는 이러한 n type layer의 doping profile을 선택적으로 형성하는 selective emitter solar cell에 관한 연구로써 SILVACO simulation을 이용하여 low Rs 영역은 고정하고 high Rs 영역의 doping depth를 가변 함으로써 high Rs 영역을 달리 형성하는 방법으로 selective emitter solar cell의 high Rs영역의 최적화에 관한 전산모사를 실시하였다. 각각의 가변조건에 따라 quantum efficiency를 통한 광학적 분석과 I-V를 통한 전기적 분석을 하여 high Rs영역을 최적화 하였다.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.