• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.327-334
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• 2016

In this paper, we propose a hardware architecture of transform and quantization for high-perfornamce HEVC(High Efficiency VIdeo Coding) encoder. HEVC transform decides the transform mode by comparing RDCost to search for the best mode of them. But, RDCost is computed using the bit-rate and distortion which is computed by transform, quantization, de-quantization, and inverse transform. Due to the many calculations and encoding time, it is hard to process high resolution and high definition image in real-time. This paper proposes the method of transform mode decision by comparing sum of coefficient after transform only. We use BD-PSNR and BD-Bitrate which is performance indicator. Based on the experimental result, We confirmed that the decision of transform mode can process images with no significant change in the image quality. We reduced hardware area by assigning different values at the same output according to the transform mode and overlapping coefficient multiplied as much as possible. Also, we raise performance by implementing sequential pipeline operation. In view of the larger process that we used compared with the process of reference paper, Our design has reduced by half the hardware area and has increased performance 2.3 times.

• Proceedings of the Korea Contents Association Conference
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• 2007.11a
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• pp.837-841
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• 2007

최근 영상을 중심으로 여러 형태의 정보를 결합하여 저장하거나 전송하는 멀티미디어가 많은 관심을 받고 있다. 현재 카메라와 관련된 동영상 캡처기술은 Motion JPEG이 주류를 이루고 있으며, 텔레비전, DMB 등의 방송 분야 및 DVD, VCR 분야에서는 MPEG-2, MPEG-4, H.264 및 WMV9 등의 압축 코덱이 채용되고 사용되고 있다. 그러나 이러한 다양한 영상 표준방식은 디코딩시 호환성 문제가 발생하게 되고 이에 따라 통합 코덱 연구가 필요하다. 이에 본 논문은 일반적 스텝 양자화외에 데드존 양자화를 사용하고 "$4{\times}4$", "$4{\times}8$", "$8{\times}4$", "$8{\times}8$"의 다양한 블록크기의 변환을 지원하는 VC-1을 기반으로 한 ITIQ C언어를 통해 시뮬레이션하고 최적화된 결과를 VHDL로 구현하여 향후 통합코덱 연구에 응용 가능하도록 연구 및 분석평가 하였다. 설계결과 4:2:0의 YCbCr포맷의 최초 $16{\times}16$블록을 복원하는데 483~510클록이 소요되었고 Xilinx XCVPC100 FF1696-6 환경에서 93,128개의 게이트 수와 71.469MHz의 동작속도를 나타내었다. 이는 640*480 크기의 컬러영상을 디코딩 하는데 프레임 당 최대 0.0074초가 소요됨을 의미하며 초당 30프레임의 영상에서도 0.222초면 디코딩이 가능한 결과이다.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2074-2079
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• 2018

Global state space's optimal policy is used for offline controller in the form of table by using Dynamic Programming. If an optimal policy table has a large amount of control data, it is difficult to use the system in a low capacity system. To resolve these problem, controller using the compressed optimal policy table is proposed in this paper. A DCT is used for compression method and the cosine function is used as a basis. The size of cosine function decreased as the frequency increased. In other words, an essential information which is used for restoration is concentrated in the low frequency band and a value of small size that belong to a high frequency band could be discarded by quantization because high frequency's information doesn't have a big effect on restoration. Therefore, memory could be largely reduced by removing the information. The compressed output is stored in memory of embedded system in offline and optimal control input which correspond to state of plant is computed by interpolation with Inverse DCT in online. To verify the performance of the proposed controller, computer simulation was accomplished with a one link inverted pendulum.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.9 s.174
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• pp.99-106
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• 2005

In recent years, vision sensors are widely used to mobile robot for navigation or exploration. The analog signal transmission of visual data being used in this area, however, has some disadvantages including noise weakness in view of the data storage. A large amount of data also makes it difficult to use this method for a mobile robot. In this paper, a digital data compressing technology based on MPEG4 which substitutes for analog technology is proposed to overcome the disadvantages by using DWT(Discreate Wavelet Transform) instead of DCT(Discreate Cosine Transform). The TI Company's DSP chip, TMS320C6711, is used for the image encoder, and the performance of the proposed method is evaluated by PSNR(Peake Signal to Noise Rates), QP(Quantization Parameter) and bitrate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1377-1384
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• 1997

We propose a new scheme to provide the fast forward and reverse(FF/R) functions to users in Video On Demand Service System. The proposed scheme is to use only I and P pictures obtained by sampling MPEG2 bit-steam. New frame raes for FF/R play are specified with parameters of MPEG2 syntrx. Bits of I and P pictures are reduced in three steps: Variable length decoding(VLD), Inverse quantization and Requantization. The proposed scheme is ecnomical in the sense that it can provide FF/R function without any additional requirement on the bandwidth and on the storage media in video server.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2071-2078
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• 2009

The first frame is encoded in intra mode which generates a larger number of bits. In addition, the first frame is used for the inter mode encoding of the following frames. Thus the intial QP (Quantization Parameter) for the first frame affects the first frame as well as the following frames. Traditionally, the initial QP is determined among four constant values only depending on the bpp. In the case of low bit rate video coding, the initial QP value is fixed to 35 regardless of the output bandwidth. Although this initialization scheme is simple, yet it is not accurate enough. An accurate intial QP prediction scheme should not only depends on bpp but also on the complexity of the video sequence and the output bandwidth. In the proposed scheme, we use a linear model because there is a linear inverse proportional relationship between the output bandwidth and the optimal intial QP. Model parameters of the model are determined depending on the spatial complexity of the first frame. It is shown by experimental results that the new algorithm can predict the optimal initial QP more accurately and generate the PSNR performance better than that of the existing JM algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.1
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• pp.84-89
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• 2019

JPEG is a most widely used standard image compression technology. This research introduces the JPEG image compression algorithm and describes each step in the compression and decompression. Image compression is the application of data compression on digital images. The DCT (discrete cosine transform) is a technique for converting a time domain to a frequency domain. First, the image is divided into 8 by 8 pixel blocks. Second, working from top to bottom left to right, the DCT is applied to each block. Third, each block is compressed through quantization. Fourth, the matrix of compressed blocks that make up the image is stored in a greatly reduced amount of space. Finally if desired, the image is reconstructed through decompression, a process using IDCT (inverse discrete cosine transform). The purpose of this research is to review all the processes of image compression / decompression using the discrete cosine transform method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.880-894
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• 1997

In this paper,we propose a new algorithm to perform DCT(Discrete Cosine Transform) withn the area reduced by prdeicting position of quantization coefficients to be zero.This proposed algorithm not only decreases the enoding time and the decoding time by reducing computation amount of FDCT(Forward DCT)and IDCT(Inverse DCT) but also increases comprossion ratio by performing each diffirent horizontal- vereical zig-zag scan assording to the calssified block size for each block on the huffiman coeing.Traditional image coding method performs the samd DCT computation and zig-zag scan over all blocks,however this proposed algorthm reduces FDCT computation time by setting to zero insted of computing DCT for quantization codfficients outside classfified block size on the encoding.Also,the algorithm reduces IDCT computation the by performing IDCT for only dequantization coefficients within calssified block size on the decoding.In addition, the algorithm reduces Run-Length by carrying out horizontal-vertical zig-zag scan approriate to the slassified block chraateristics,thus providing the improverment of the compression ratio,On the on ther hand,this proposed algorithm can be applied to 16*16 block processing in which the compression ratio and the image resolution are optimal but the encoding time and the decoding time take long.Also,the algorithm can be extended to motion image coding requirng real time processing.