• Title/Summary/Keyword: interpolation decoding

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FAST UNIQUE DECODING OF PLANE AG CODES

  • Lee, Kwankyu
    • Honam Mathematical Journal
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    • v.35 no.4
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    • pp.793-808
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    • 2013
  • An interpolation-based unique decoding algorithm of Algebraic Geometry codes was recently introduced. The algorithm iteratively computes the sent message through a majority voting procedure using the Gr$\ddot{o}$bner bases of interpolation modules. We now combine the main idea of the Guruswami-Sudan list decoding with the algorithm, and thus obtain a hybrid unique decoding algorithm of plane AG codes, significantly improving the decoding speed.

UNIQUE DECODING OF PLANE AG CODES REVISITED

  • Lee, Kwankyu
    • Journal of applied mathematics & informatics
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    • v.32 no.1_2
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    • pp.83-98
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    • 2014
  • We reformulate an interpolation-based unique decoding algorithm of AG codes, using the theory of Gr$\ddot{o}$bner bases of modules on the coordinate ring of the base curve. The conceptual description of the reformulated algorithm lets us better understand the majority voting procedure, which is central in the interpolation-based unique decoding. Moreover the smaller Gr$\ddot{o}$bner bases imply smaller space and time complexity of the algorithm.

A COMPLEXITY-REDUCED INTERPOLATION ALGORITHM FOR SOFT-DECISION DECODING OF REED-SOLOMON CODES

  • Lee, Kwankyu
    • Journal of applied mathematics & informatics
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    • v.31 no.5_6
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    • pp.785-794
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    • 2013
  • Soon after Lee and O'Sullivan proposed a new interpolation algorithm for algebraic soft-decision decoding of Reed-Solomon codes, there have been some attempts to apply a coordinate transformation technique to the new algorithm, with a remarkable complexity reducing effect. In this paper, a conceptually simple way of applying the transformation technique to the interpolation algorithm is proposed.

Reducing Decoding Complexity by Improving Motion Field Using Bicubic and Lanczos Interpolation Techniques in Wyner-Ziv Video Coding

  • Widyantara, I Made O.;Wirawan, Wirawan;Hendrantoro, Gamantyo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.6 no.9
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    • pp.2351-2369
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    • 2012
  • This paper describes interpolation method of motion field in the Wyner-Ziv video coding (WZVC) based on Expectation-Maximization (EM) algorithm. In the EM algorithm, the estimated motion field distribution is calculated on a block-by-block basis. Each pixel in the block shares similar probability distribution, producing an undesired blocking artefact on the pixel-based motion field. The proposed interpolation techniques are Bicubic and Lanczos which successively use 16 and 32 neighborhood probability distributions of block-based motion field for one pixel in k-by-k block on pixel-based motion field. EM-based WZVC codec updates the estimated probability distribution on block-based motion field, and interpolates it to pixel resolution. This is required to generate higher-quality soft side information (SI) such that the decoding algorithm is able to make syndrome estimation more quickly. Our experiments showed that the proposed interpolation methods have the capability to reduce EM-based WZVC decoding complexity with small increment of bit rate.

An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding

  • Jin, Xianzhe;Ryoo, Kwangki
    • Journal of information and communication convergence engineering
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    • v.11 no.2
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    • pp.118-123
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    • 2013
  • This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

Improved Physical Layer Implementation of VANETs

  • Khan, Latif Ullah;Khattak, M. Irfan;Khan, Naeem;Khan, Atif Sardar;Shafi, M.
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.3
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    • pp.142-152
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    • 2014
  • Vehicular Ad-hoc Networks (VANETs) are comprised of wireless mobile nodes characterized by a randomly changing topology, high mobility, availability of geographic position, and fewer power constraints. Orthogonal Frequency Division Multiplexing (OFDM) is a promising candidate for the physical layer of VANET because of the inherent characteristics of the spectral efficiency and robustness to channel impairments. The susceptibility of OFDM to Inter-Carrier Interference (ICI) is a challenging issue. The high mobility of nodes in VANET causes higher Doppler shifts, which results in ICI in the OFDM system. In this paper, a frequency domain com-btype channel estimation was used to cancel out ICI. The channel frequency response at the pilot tones was estimated using a Least Square (LS) estimator. An efficient interpolation technique is required to estimate the channel at the data tones with low interpolation error. This paper proposes a robust interpolation technique to estimate the channel frequency response at the data subcarriers. The channel induced noise tended to degrade the Bit Error Rate (BER) performance of the system. Parallel concatenated Convolutional codes were used for error correction. At the decoding end, different decoding algorithms were considered for the component decoders of the iterative Turbo decoder. A performance and complexity comparison among the various decoding algorithms was also carried out.

Distributed Video Coding Frame Interpolation using Dominant MV (우세 움직임 벡터를 이용한 Distributed Video Coding 화면 보간)

  • Choi, Seong-Hyun;Lee, Seong-Won
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2010.07a
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    • pp.422-423
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    • 2010
  • 최근 Encoding과정에 비용이 많이 들어가는 MPEG계열의 압축 기술과 다르게 Encoding과 Decoding에 적절히 비용을 분산시키는 Distributed Video Coding(DVC)에 대한 연구가 활발히 진행되고 있다. 이는 휴대용 멀티미디어 기기들의 발전으로 영상 압축에 대한 비용을 분산시킬 필요가 발생했기 때문이다. 이때 Decoding과정에서 생성되는 side information의 정확성은 Winer-Ziv 프레임 복원에 대한 parity비트에 영향을 줘 압축 성능에 큰 영향을 준다. 이에 본 논문은 DVC에 사용할 수 있는 보다 정확한 Frame Interpolation방법을 제안한다. 단일 방향 예측을 통해 움직임 벡터를 생성하고 비어있는 공간에 대해 분산을 이용, Dominant MV와 픽셀평균값을 이용하여 프레임을 생성한다. 이는 기존 frame interpolation방법에 비해 비용이 적게 들고, 화질은 그대로 유지할수 있는 장점이 있다. 이를 확인하기 위해 DVC기법에 사용되는 frame interpolation에 제안하는 알고리즘을 적용하여 실험을 진행하였으며 다른 알고리즘들과 비교해 화질은 유지하고 계산량은 줄일수 있었다.

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Area-efficient Interpolation Architecture for Soft-Decision List Decoding of Reed-Solomon Codes (연판정 Reed-Solomon 리스트 디코딩을 위한 저복잡도 Interpolation 구조)

  • Lee, Sungman;Park, Taegeun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.3
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    • pp.59-67
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    • 2013
  • Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

New Video Compression Method based on Low-complexity Interpolation Filter-bank (저 복잡도 보간 필터 뱅크 기반의 새로운 비디오 압축 방법)

  • Nam, Jung-Hak;Jo, Hyun-Ho;Sim, Dong-Gyu;Choi, Byeong-Doo;Cho, Dae-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.5
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    • pp.165-174
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    • 2010
  • The H.264/AVC standard obtained better performance than previous compression standards, but it also increased the computational complexity of CODEC simultaneously. Various techniques recently included at the KTA software developed by VCEG also were increasing its complexity. Especially adaptive interpolation filter has more complexity than two times due to development for coding efficiency. In this paper, we propose low-complexity filter bank to improve speed up of decoding and coding gain. We consists of filter bank of a fixed-simple filter for low-complexity and adaptive interpolation filter for high coding efficiency. Then we compensated using optimal filter at each macroblock-level or frame-level. Experimental results shows a similar coding efficiency compared to existing adaptive interpolation filter and decoding speed of approximately 12% of the entire decoder gained.

Multi-resolution Lossless Image Compression for Progressive Transmission and Multiple Decoding Using an Enhanced Edge Adaptive Hierarchical Interpolation

  • Biadgie, Yenewondim;Kim, Min-sung;Sohn, Kyung-Ah
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.12
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    • pp.6017-6037
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    • 2017
  • In a multi-resolution image encoding system, the image is encoded into a single file as a layer of bit streams, and then it is transmitted layer by layer progressively to reduce the transmission time across a low bandwidth connection. This encoding scheme is also suitable for multiple decoders, each with different capabilities ranging from a handheld device to a PC. In our previous work, we proposed an edge adaptive hierarchical interpolation algorithm for multi-resolution image coding system. In this paper, we enhanced its compression efficiency by adding three major components. First, its prediction accuracy is improved using context adaptive error modeling as a feedback. Second, the conditional probability of prediction errors is sharpened by removing the sign redundancy among local prediction errors by applying sign flipping. Third, the conditional probability is sharpened further by reducing the number of distinct error symbols using error remapping function. Experimental results on benchmark data sets reveal that the enhanced algorithm achieves a better compression bit rate than our previous algorithm and other algorithms. It is shown that compression bit rate is much better for images that are rich in directional edges and textures. The enhanced algorithm also shows better rate-distortion performance and visual quality at the intermediate stages of progressive image transmission.