• 제목/요약/키워드: interleaving

검색결과 257건 처리시간 0.024초

A Dynamic Packet Recovery Mechanism for Realtime Service in Mobile Computing Environments

  • Park, Kwang-Roh;Oh, Yeun-Joo;Lim, Kyung-Shik;Cho, Kyoung-Rok
    • ETRI Journal
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    • 제25권5호
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    • pp.356-368
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    • 2003
  • This paper analyzes the characteristics of packet losses in mobile computing environments based on the Gilbert model and then describes a mechanism that can recover the lost audio packets using redundant data. Using information periodically reported by a receiver, the sender dynamically adjusts the amount and offset values of redundant data with the constraint of minimizing the bandwidth consumption of wireless links. Since mobile computing environments can be often characterized by frequent and consecutive packet losses, loss recovery mechanism need to deal efficiently with both random and consecutive packet losses. To achieve this, the suggested mechanism uses relatively large, discontinuous exponential offset values. That gives the same effect as using both the sequential and interleaving redundant information. To verify the effectiveness of the mechanism, we extended and implemented RTP/RTCP and applications. The experimental results show that our mechanism, with an exponential offset, achieves a remarkably low complete packet loss rate and adapts dynamically to the fluctuation of the packet loss pattern in mobile computing environments.

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Advanced ZigBee Baseband Processor with Variable Data Rates for Internet-of-things Applications

  • Hwang, Hyunsu;Jang, Soohyun;Lee, Seongjoo;Jung, Yunho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권1호
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    • pp.56-64
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    • 2017
  • In this paper, an advanced ZigBee (AZB) system for internet-of-things (IoT) applications is proposed which can support various data rates from 31.25 Kbps to 2 Mbps, and the implementation results of the AZB baseband processor are presented. Repetition coding for 32-chip direct-sequence spread spectrum (DSSS) symbol is applied for low rates under 250 Kbps to extend the coverage. Convolution coding, puncturing, and interleaving for non-DSSS symbol are performed for high rates from 500 Kbps to 2 Mbps for multi-media services. Simulation results show that the coverage increases at the rate of 51.8-77.3% for various environments compared with IEEE 802.15.4 ZigBee. AZB baseband processor was implemented in 180 nm CMOS process and total gate counts are 260K with the size of $5.8mm^2$.

Side Information에 오경보와 미탐지가 존재할 띠 저속 주파수 도약 시스템의 BER분석 (Analysis of BER in Slow Frequency-Hopping System with False Alarm and Miss in Side Information)

  • 한상진;김용철;강경원;윤희철
    • 한국통신학회논문지
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    • 제26권11B호
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    • pp.1556-1564
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    • 2001
  • SFH (저속 주파수 도약) 시스템에서는 주파수 슬롯의 히트에 대처하기 위하여, 보통 Reed-Solomon 부호와 인터리빙을 사용한다. SI (Side Information)를 이용하여 히트되는 심볼을 이레이져 처리하는 EE (Errors-and-Erasure) 복호 방식의 패킷 단위 오류 율에 대해서는 많은 분석이 이루어졌으나, 오경보와 미탐지가 발생하는 불완전한 Sl를 이용할 때의 BER 성능에 대해서는 Monte Carlo 시뮬레이션에 의한 분석만이 행하여 졌을 뿐이다. 본 논문에서는 테스트 패턴을 사용하여 얻은 SI에 오경보와 미탐지가 존재하는 상황에서 SFH 시스템의 BER을 추정하는수식을 제안한다. Sl에 오류가 존재하지 않는다는 가정을 사용하지 않고, 심볼의 비트 오류의 수를 추정하여 SFH시스템의 BER을 추정한 값과 시뮬레이션으로 얻어진 BER을 비교하여 두 결과가 일치함을 확인하였다. 또한 기존의 연구에서 얻은 수식들은 본 연구에서 제안하는 수식으로부터 유도할 수 있음을 보였다.

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상관 페이딩 채널에서 사전스위칭 다이버시티를 갖는 트렐리스 부호화 변조 (Trellis-Coded Modulation with Preswitching Diversity for Correlated Fading Channel)

  • Hahm, Young-Kwon
    • 한국전자파학회논문지
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    • 제7권4호
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    • pp.310-319
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    • 1996
  • 페이딩 채널에 적합하도록 설계된 TCM은 채널으이 페이딩 상관을 없애는 이상적인 인터리버를 사용한다는 가정하에 설계된방식으로, 저속 페이딩 채널에서 유한 크기의 인터리버를 사용할 수 경우에 페이딩을 잘 분산시킬 수 없기 때문에 부호화 변조 시스템의 성능이 급격히 떨어진다. 이런한 성능 저하를 개선하기 위하여 송신 안테나의 사전 스위칭에 의하여 인터리빙 효과를 얻을 수 있는 방식을 제안하였으며, 이러한 방식의 성능 개선을 해석과 시뮬레이션에 의하여 보여 준다. 결고를 보면 느린 페이딩 환경에서 상당한 성능 개선이 있었으며, 페이딩이 빨라지면 기존의 방식과 같은 성능을 갖는다.

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Two-Phase Hybrid Forward Convertor with Series-Parallel Auto-Regulated Transformer Windings and a Common Output Inductor

  • Wu, Xinke;Chen, Hui
    • Journal of Power Electronics
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    • 제13권5호
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    • pp.757-765
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    • 2013
  • For conventional interleaved two-phase forward converters with a common output inductor, the maximum duty cycle is 0.5, which limits the voltage range and increases the difficulty of the transformer's optimization. A new two-phase hybrid forward converter with series-parallel auto-regulated transformer windings is presented in this paper. With interleaved control signals for the two phases, the secondary windings of the transformers can work in series when the duty cycle is larger than 0.5, and they can work in parallel when duty cycle is lower than 0.5. Therefore, the maximum duty cycle is extended and the turns ratio of the transformer can be optimized. Duty cycle dependent auto-regulated windings result in the steady states of the converter being different in different duty cycle ranges (D>0.5 and D<0.5). Fortunately, the steady state gains of the proposed hybrid converter are identical at different duty cycle ranges, which means a stepless shift between two states. A prototype is built to verify the theoretical analysis. A conventional control loop is compatible for the whole input voltage range and load range thanks to the stepless shifting between the different duty cycle ranges.

PPS 제어기법을 적용한 48V-400V 비절연 양방향 DC-DC컨버터 (A 48V-400V Non-isolated Bidirectional Soft-switching DC-DC Converter for Residential ESS)

  • 정현주;권민호;최세완
    • 전력전자학회논문지
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    • 제23권3호
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    • pp.190-198
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    • 2018
  • This paper proposes a nonisolated, bidirectional, soft-switching DC - DC converter with PWM plus phase shift (PPS) control. The proposed converter has an input-parallel/output-series configuration and can achieve the interleaving effect and high voltage gains, resulting in decreased voltage ratings in all related devices. The proposed converter can operate under zero-voltage switching (ZVS) conditions for all switches in continuous conduction mode. The power flow of the proposed converter can be controlled by changing the phase shift angle, and the duty is controlled to balance the voltage of four high voltage side capacitors. The PPS control device of the proposed converter is simple in structure and presents symmetrical switching patterns under a bidirectional power flow. The PPS control also ensures ZVS during charging and discharging at all loads and equalizes the voltage ratings of the output capacitors and switches. To verify the validity of the proposed converter, an experimental investigation of a 2 kW prototype is performed in both charging and discharging modes under different load conditions and a bidirectional power flow.

QoS-Oriented Solutions for Satellite Broadcasting Systems

  • Vargas, Aharon;Gerstacker, Wolfgang H.;Breiling, Marco
    • Journal of Communications and Networks
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    • 제12권6호
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    • pp.558-567
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    • 2010
  • In this paper, we analyze the capability of satellite broadcasting systems to offer different levels of quality of service (QoS). We focus on the European telecommunications standards institute satellite digital radio and digital video broadcasting satellite handheld (DVB-SH) standards, which have recently been proposed for satellite broadcasting communications. We propose a strategy to provide different levels of QoS for the DVB-SH standard on the basis of an extension of the interleaving scheme, referred to as molded interleaver, which supports low latency service requirements for interactive services. An extensive analysis based on laboratory measurements shows the benefits of this solution. We also present a multilevel coding (MLC) scheme with multistage decoding designed for broadcasting communications as an alternative to the existing standards, where services with different levels of QoS are provided. We present a graphical method based on mutual information for the design and evaluation of MLC systems used for broadcasting communications. Extensive simulations for a typical satellite channel show the viability of the proposed MLC scheme. Finally, we introduce multidimensional constellations in the proposed MLC scheme in order to increase the number of different protection levels.

Unequal Error Protection and Error Concealment Schemes for the Transmission of H.263 Video over Mobile Channels

  • 홍원기;고성재
    • 전기전자학회논문지
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    • 제2권2호
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    • pp.285-293
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    • 1998
  • This paper presents unequal error protection and error concealment techniques far robust H.263 video transmission over mobile channels. The proposed error protection scheme has three major features. First, it has the capability of preventing the loss of synchronization information in H.263 video stream as much as possible that the H.263 decoder can resynchronize at the next decoding point, if errors are occurred. Secondly, it employs an unequal error protection scheme to support variable coding rates using rate compatible punctured convolutional (RCPC) codes, dividing the encoded stream into two classes. Finally, a macroblock-interleaving scheme is employed in order to minimize the corruption of consecutive macroblocks due to burst errors, which can make a proper condition for error concealment. In addition, to minimize the spatial error propagations due to the variable length codes, a fast resynchronization scheme at the group of block layer is developed for recovering subsequent error-free macroblocks following the damaged macroblock. futhermore, error concealment techniques based on both side match criterion and overlapped block motion compensation (OBMC) are employed at the source decoder so that it can not only recover the lost macroblock more accurately, but also reduce blocking artifacts. Experimental results show that the proposed scheme can be an effective error protection scheme since proper video quality can be maintained under various channel bit error rates.

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비대칭 신호점에 의한 부호화된 16-QAM의 이동 무선 채널에서의 BER 성능 개선에 관한 연구 (An Improvement of BER Performance for Coded 16-QAM over Mobile Communication Channel by Asymmetric Signal Constellation)

  • 김태헌;하덕호
    • 한국전자파학회논문지
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    • 제8권2호
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    • pp.197-206
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    • 1997
  • 본 논문에서는 페이딩 채널에서 16-QAM 통신 방식의 BER을 개선하는 방법을 제안하고자 한다. 페이딩에 의한 BER 성능 열화를 극복하기위하여 대역폭 확장없이 우수한 코딩 이득을 얻을 수 있는 트렐리스 부호 변조방식을 16-QAM에 적용하였다. 또한 이동통신 환경의 주요 성능 열화 요인인 연집오류를 극복하기위해 인터리빙/디인터리빙기법을 연구되고 있는 시스템에 적용하였다. 특히, 비대칭적 신호점 분포를 적용하여 컴퓨터 시뮬레이션한 결과 $10^{-4}$ 근처에서 약 1dB의 성능 개선을 가져왔다.

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Analysis and Control of a Modular MV-to-LV Rectifier based on a Cascaded Multilevel Converter

  • Iman-Eini, Hossein;Farhangi, Shahrokh;Khakbazan-Fard, Mahboubeh;Schanen, Jean-Luc
    • Journal of Power Electronics
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    • 제9권2호
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    • pp.133-145
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    • 2009
  • In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.