• ETRI Journal
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• v.25 no.5
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• pp.356-368
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• 2003

This paper analyzes the characteristics of packet losses in mobile computing environments based on the Gilbert model and then describes a mechanism that can recover the lost audio packets using redundant data. Using information periodically reported by a receiver, the sender dynamically adjusts the amount and offset values of redundant data with the constraint of minimizing the bandwidth consumption of wireless links. Since mobile computing environments can be often characterized by frequent and consecutive packet losses, loss recovery mechanism need to deal efficiently with both random and consecutive packet losses. To achieve this, the suggested mechanism uses relatively large, discontinuous exponential offset values. That gives the same effect as using both the sequential and interleaving redundant information. To verify the effectiveness of the mechanism, we extended and implemented RTP/RTCP and applications. The experimental results show that our mechanism, with an exponential offset, achieves a remarkably low complete packet loss rate and adapts dynamically to the fluctuation of the packet loss pattern in mobile computing environments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.56-64
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• 2017

In this paper, an advanced ZigBee (AZB) system for internet-of-things (IoT) applications is proposed which can support various data rates from 31.25 Kbps to 2 Mbps, and the implementation results of the AZB baseband processor are presented. Repetition coding for 32-chip direct-sequence spread spectrum (DSSS) symbol is applied for low rates under 250 Kbps to extend the coverage. Convolution coding, puncturing, and interleaving for non-DSSS symbol are performed for high rates from 500 Kbps to 2 Mbps for multi-media services. Simulation results show that the coverage increases at the rate of 51.8-77.3% for various environments compared with IEEE 802.15.4 ZigBee. AZB baseband processor was implemented in 180 nm CMOS process and total gate counts are 260K with the size of $5.8mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1556-1564
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• 2001

Reed-Solomon code, block interleaving and SI (side information) are frequently used in SFH (slow frequency hopping) system. Erasing those symbols in the hit frequency slot greatly increases the error connection capacity. Packet error rate has been the major performance measure for SFH system. The analysis of BER has been limited to the case of perfect Sl, in which neither miss nor false alarm exists. BER with imperfect Sl has been obtained only by Monte Carlo simulation. In this paper, we present a unified solution to estimate BER with imperfect Sl. It is shown that previous formulae for packet error rate or BER with perfect Sl are special cases in the proposed solution. The computed BER with false alarm and miss of frequency hit is verified by comparing with the simulation result.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.4
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• pp.310-319
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• 1996

The existing coders used in the fading channels are designed under the assumption that the ideal interleaver, which removes the fading correlation of the channel, is used. With the non-ideal interleaver of finite size, however, the performance of the coded modulation system degrades rapidly when the fading is very slow. A new method which achieves interleaving effects by switching the transmitter antennas is suggested to improve the performance even in the slow fading. The performance of the new system is analyzed. The results show significant performance improvement in the slow fading and at least no deterioration in the fast fading over the existing systems.

• Journal of Power Electronics
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• v.13 no.5
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• pp.757-765
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• 2013

For conventional interleaved two-phase forward converters with a common output inductor, the maximum duty cycle is 0.5, which limits the voltage range and increases the difficulty of the transformer's optimization. A new two-phase hybrid forward converter with series-parallel auto-regulated transformer windings is presented in this paper. With interleaved control signals for the two phases, the secondary windings of the transformers can work in series when the duty cycle is larger than 0.5, and they can work in parallel when duty cycle is lower than 0.5. Therefore, the maximum duty cycle is extended and the turns ratio of the transformer can be optimized. Duty cycle dependent auto-regulated windings result in the steady states of the converter being different in different duty cycle ranges (D>0.5 and D<0.5). Fortunately, the steady state gains of the proposed hybrid converter are identical at different duty cycle ranges, which means a stepless shift between two states. A prototype is built to verify the theoretical analysis. A conventional control loop is compatible for the whole input voltage range and load range thanks to the stepless shifting between the different duty cycle ranges.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.3
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• pp.190-198
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• 2018

This paper proposes a nonisolated, bidirectional, soft-switching DC - DC converter with PWM plus phase shift (PPS) control. The proposed converter has an input-parallel/output-series configuration and can achieve the interleaving effect and high voltage gains, resulting in decreased voltage ratings in all related devices. The proposed converter can operate under zero-voltage switching (ZVS) conditions for all switches in continuous conduction mode. The power flow of the proposed converter can be controlled by changing the phase shift angle, and the duty is controlled to balance the voltage of four high voltage side capacitors. The PPS control device of the proposed converter is simple in structure and presents symmetrical switching patterns under a bidirectional power flow. The PPS control also ensures ZVS during charging and discharging at all loads and equalizes the voltage ratings of the output capacitors and switches. To verify the validity of the proposed converter, an experimental investigation of a 2 kW prototype is performed in both charging and discharging modes under different load conditions and a bidirectional power flow.

• Journal of Communications and Networks
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• v.12 no.6
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• pp.558-567
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• 2010

In this paper, we analyze the capability of satellite broadcasting systems to offer different levels of quality of service (QoS). We focus on the European telecommunications standards institute satellite digital radio and digital video broadcasting satellite handheld (DVB-SH) standards, which have recently been proposed for satellite broadcasting communications. We propose a strategy to provide different levels of QoS for the DVB-SH standard on the basis of an extension of the interleaving scheme, referred to as molded interleaver, which supports low latency service requirements for interactive services. An extensive analysis based on laboratory measurements shows the benefits of this solution. We also present a multilevel coding (MLC) scheme with multistage decoding designed for broadcasting communications as an alternative to the existing standards, where services with different levels of QoS are provided. We present a graphical method based on mutual information for the design and evaluation of MLC systems used for broadcasting communications. Extensive simulations for a typical satellite channel show the viability of the proposed MLC scheme. Finally, we introduce multidimensional constellations in the proposed MLC scheme in order to increase the number of different protection levels.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.285-293
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• 1998

This paper presents unequal error protection and error concealment techniques far robust H.263 video transmission over mobile channels. The proposed error protection scheme has three major features. First, it has the capability of preventing the loss of synchronization information in H.263 video stream as much as possible that the H.263 decoder can resynchronize at the next decoding point, if errors are occurred. Secondly, it employs an unequal error protection scheme to support variable coding rates using rate compatible punctured convolutional (RCPC) codes, dividing the encoded stream into two classes. Finally, a macroblock-interleaving scheme is employed in order to minimize the corruption of consecutive macroblocks due to burst errors, which can make a proper condition for error concealment. In addition, to minimize the spatial error propagations due to the variable length codes, a fast resynchronization scheme at the group of block layer is developed for recovering subsequent error-free macroblocks following the damaged macroblock. futhermore, error concealment techniques based on both side match criterion and overlapped block motion compensation (OBMC) are employed at the source decoder so that it can not only recover the lost macroblock more accurately, but also reduce blocking artifacts. Experimental results show that the proposed scheme can be an effective error protection scheme since proper video quality can be maintained under various channel bit error rates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.2
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• pp.197-206
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• 1997

The purpose of this paper is to propose an improvement method of BER for coded 16QAM over Rayleigh fading channel. To overcome the BER degradation due to the fading under mobile communication, we apply trellis coded modulation technique which is efficient to get a coding gain without the expansion of bandwidth. Especially, to minimize the burst error which are the main factor of the BER degradation for mobile communication systems, we apply interleaving/deinterleaving method to the studying system. Also we apply asymmetric signal mapping methods to this TCM scheme. From the computer simulation, BER performance of asymmetric case has achieved about 1 dB improvement of about $10^{-4}$, compared to the traditional symmetric case.

• Journal of Power Electronics
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• v.9 no.2
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.