• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Journal of Advanced Marine Engineering and Technology
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• 제33권5호
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• pp.746-755
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• 2009

Recently, NMEA2000 became the de facto standard of the communication protocol for the instrument level network in vessels, and it is anticipated that most of the vessels will be equipped with the sensors and actuators based on this protocol. The conventional serial communication specifications such as RS-232, RS-485, or even NMEA0183 are single-talker/multiple-listener and interconnection among multiple sensors and/or actuators usually results in a bundle of wires. On the other hand, NMEA2000 is a true bus type(multiple-talker/multiple-listener) protocol and theoretically up to 256 instruments can be hot-plugged. With the advent of the protocol, it is necessary to consider a new type of monitoring system for the instruments in vessels: In most traditional serial communication environments, a dedicated monitor or user interface was necessary for each sensor or actuator as it was simply not easy to collect data in a single place. With NMEA2000, the collection of various types of information is simple. An embedded system can be employed to combine, to arrange and to display informations from various types of devices. Assuming that the actuators and sensors on a vessel are interconnected by NMEA2000 standard, we devise a tentative interactive vessel monitoring system in which the following 4 kinds of informations are collected and delivered: the navigation, engine, weather and tanks informations.

• 정보처리학회논문지A
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• 제8A권2호
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• pp.147-156
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• 2001

A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전력기술부문
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• pp.137-140
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• 2002

This paper describes the effect of distributed generations (DG) on the bus protection scheme. When the generating capacity of DG is larger than 3 MVA totally, DG are generally connected to the 22.9 kV bus directly with the dedicated line. Due to the fault current contribution of DG, the overcurrent protective relay that have conventional set value cannot detect the fault occurred in distribution power network with DG. Therefore. the impacts from interconnection of DG on the overcurrent protective relay for bus protection should be accurately assessed and mitigated. Simulation results show that it would be necessary to modify the overcurrent protective relay set value for protecting the bus according to the generating capacity of DG.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권5호
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• pp.1606-1623
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• 2015

Optical switching will be applied in datacenter networks because electronic switching is costly and power-consuming. In this paper, considering the ring-based interconnection using optical switching in the core of a datacenter, we study the home circuit (HC) construction for the labeled optical burst switching with home circuit (LOBS-HC), a new paradigm trying to share wavelengths among the HCs from the same source. In particular, aiming to construct HCs dynamically and properly, a scheme named optimal path matching and symmetric HC matching (OPM-SHM) is proposed. The main idea of OPM-SHM is to dynamically construct HCs by sharing wavelength(s) not only among the same-source HCs but also with symmetric HCs which have different sources other than the original LOBS-HC features. The simulation results demonstrate that OPM-SHM achieves better performance than some other methods in terms of burst loss rate and wavelength utilization of physical links. More specially, it maintains good load balancing for the datacenter network using an LOBS-HC ring. In addition, due to the symmetric feature of SHM, the proposed scheme can decrease the upper bound of the average hop count of the routing paths to half of the ring size.

• 한국산학기술학회논문지
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• 제10권1호
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• pp.81-90
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• 2009

전력산업의 구조개편과 더불어 분산전원의 배전계통연계운용 및 전력품질이 전력회사의 배전사업자, 구역전기사업자, 전기공급 신뢰도와 밀접한 관계에 있는 산업용 수용가들에게 많은 관심을 불러일으키고 있다. 이러한 주변정세는 차세대의 배전계통이 다수의 Micro-grid들로 구성될 것이라고 하는 예상을 전문가들로부터 제기되기에 이르렀다. 그러나, 제안된 Micro-grid는 몇몇의 분산전원과 전력품질을 보상하는 기기, 그리고 통신제어설비와 부하들로 구성된다는 기본적인 내용에 지나지 않는다 따라서, 본 논문에서는 수용가에 고신뢰 고품질의 전력공급을 가능하게 하는 차세대 전력공급네트워크인 Micro-grid의 적정전압유지를 위한 자율분산협조 운용제어 알고리즘을 제안한다.

• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• 한국정보처리학회논문지
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• 제5권12호
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• pp.3099-3108
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• 1998

본 논문에서는 새로운 다중 컴퓨터의 위상으로 하이퍼-스타 그래프를 제안하고, 하이퍼-스타 그래프에 대하여 주요 망 척도인 분지수, 연결도, 확장성, 라우팅, 지름, 임베딩 등의 특징을 분석한다. 하이퍼-스타 그래프 HS(2n,n)에 에지를 한 개 추가한 folded 하이퍼-스타 그래프 FHS(2n,n)은 2nCn개의 노드를 갖고 널리 알려진 상호 연결망인 하이퍼큐브에 비해 상대적으로 분지수와 지름이 작은 값을 갖는 연결망이다. Folded 하이퍼-스타 그래프 FHS(2n,n)가 하이퍼큐브 Qn이 같은 노드 수를 가질 때 분지수$\times$지름에 대한 척도에 있어서 은 n2/2보다 작고, 하이퍼큐브 Qn와 그의 변형들보다 연결망의 망 비용에 있어서 우수함을 의미한다. 또한 하이퍼큐브 Qn과 n$\times$n 토러스를 하이퍼-스타 그래프 HS(2n,n)에 연장비율 2에 임베딩하는 방법을 보인다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2016년도 춘계학술발표대회
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• pp.51-54
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• 2016

NTB는 transparent bridge와 공통적으로 독립적인 PCI bus(PCI 또는 PCI Express bus)에 대해서 데이터 전송 경로(path)를 제공한다는 점에서 기능적으로 유사하다. 그러나, NTB와 transparent bridge 간의 가장 큰 차이점은 NTB가 사용될 경우에 bridge의 하향부분(downstream side)에 위치한 장치들은 상향부분(upstream side)에서는 보이지 않는다는 점이다. 이는 bridge의 하향부분(downstream side)에 위치한 인텔리전트(intelligent)한 제어기(예를들면 CPU를 포함하는 컴퓨터)가 자신의 downstream side에 위치하는 서브시스템 내 각종 장치들을 독립적으로 관리할 수 있다는 점이다. NTB는 또한 첫 번째 호스트(primary host)의 PCI bus로 구성된 서브시스템(subsystem) 계층구조(hierarchy)에 두 번째 호스트(secondary host)를 연결하는 데 사용될 수 있다. 이는 두 시스템간 통신을 가능하도록 하는 반면, 두 시스템을 서로 격리시키는 효과도 발생한다. 즉, NTB는 일반적으로 도어벨(doorbell)을 통해서 bridge의 다른 편에 위치한 장치에 대해서 인터럽트를 보낼 수 있으며, 또한, scratchpad 레지스터를 보유하고 있어 bridge의 양측에서 데이터를 상호 공유함으로써 interprocessor communication 할 수 있다.

• 전기학회논문지
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• 제58권9호
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• pp.1674-1680
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• 2009

This paper proposes an autonomous fault determination, fault zone isolation and fault restoration strategy based on the ethernet communication as a new attempt to solve the problem the of the existing central control method. In proposed method, The FRTU(Feeder Remote Terminal Unit)s on the feeder determines autonomously where the faulted zone is by exchanging the voltage and current information with neighbor FRTUs based on the network communication, and then separates the faulted zone in an nil-voltage status to make the protective device to reclose successively. In particular, the minimization of outage time and relational load balancing is archived by each interconnection switch which determines autonomously the load zone to be allocated among those zones after the sound outage zones was separated individually. Finally, to show effectiveness of the proposed fault restoration strategy, the several fault cases are simulated for the test distribution system, and the load balancing index of the proposed solution is compared with all of feasible solutions.