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Single-Chip Microprocessor Control for Switched Reluctance Motor Drive

  • Hao Chen;Ahn, Jin-Woo
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • v.2B no.4
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    • pp.207-213
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    • 2002
  • The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

Development and Analyses of Xen based Dynamic Binary Instrumentation using Intel VT (Intel VT 기술을 이용한 Xen 기반 동적 악성코드 분석 시스템 구현 및 평가)

  • Kim, Tae-Hyoung;Kim, In-Hyuk;Eom, Young-Ik;Kim, Won-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.37 no.5
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    • pp.304-313
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    • 2010
  • There are several methods for malware analyses. However, it is difficult to detect malware exactly with existing detection methods. Especially, malware with strong anti-debugging facilities can detect analyzer and disturb their analyses. Furthermore, it takes too much time to analyze malware. In order to resolve these problems of current analyzers, more improved analysis scheme is required. This paper suggests a dynamic binary instrumentation which supports the instruction analysis and the memory access tracing. Additionally, by supporting the API call tracing with the DLL loading analysis, our system establishes the foundation for analyzing various executable codes. Based on Xen, full-virtualization environment is built using Intel's VT technology. Windows XP can be used as a guest. We analyze representative malware using several functions of our system, and show the accuracy and efficiency enhancements in binary analyses capability of our system.

Coming To America: The Use of 28 U.S.C. § 1782

  • Robertson, Ann Ryan;Friedman, Scott L.
    • Journal of Arbitration Studies
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    • v.25 no.3
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    • pp.59-90
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    • 2015
  • Since 1855, the federal courts of the United States have been empowered to assist in the gathering of evidence for use before foreign tribunals. Today, the source of that authority is 28 U.S.C. ${\S}1782$ which permits the courts to order a person "to give [ ] testimony... or to produce a document ... for use in a proceeding in a foreign or international tribunal${\cdots}$ ." It was generally assumed, until the United States Supreme Court's decision of Intel Corp. v. Advanced Micro Devices, Inc. in 2004, that arbitration tribunals were not "foreign tribunals" for purposes of 28 U.S.C. ${\S}1782$. While the issue in Intel did not involve an arbitration tribunal, a statement by the Supreme Court in dicta has called into question the exact parameters of the words "foreign tribunal," resulting in a split of opinion among the federal courts of the United States. This article explores the legislative history of 28 U.S.C. ${\S}1782$, examines the United States Supreme Court decision in Intel, and discusses the split among the courts of the United States regarding the interpretation of "foreign tribunal." The article further surveys emerging issues: is an arbitration tribunal in a case involving foreign parties and seated in the United States a "foreign tribunal"; does agreeing to the use of the IBA Rules on the Taking of Evidence in International Arbitration circumscribe the use of 28 U.S.C. ${\S}1782$; can a party be ordered to produce documents located outside the United States; and is there a role for judicial estoppel in determining whether an application pursuant to 28 U.S.C. ${\S}1782$ should be granted?

A Study on Dynamic Code Analysis Method using 2nd Generation PT(Processor Trace) (2세대 PT(Processor Trace)를 이용한 동적 코드분석 방법 연구)

  • Kim, Hyuncheol
    • Convergence Security Journal
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    • v.19 no.1
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    • pp.97-101
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    • 2019
  • If the operating system's core file contains an Intel PT, the debugger can not only check the program state at the time of the crash, but can also reconfigure the control flow that caused the crash. We can also extend the execution trace scope to the entire system to debug kernel panics and other system hangs. The second-generation PT, the WinIPT library, includes an Intel PT driver with additional code to run process and core-specific traces through the IOCTL and registry mechanisms provided by Windows 10 (RS5). In other words, the PT trace information, which was limited access only by the first generation PT, can be executed by process and core by the IOCTL and registry mechanism provided by the operating system in the second generation PT. In this paper, we compare and describe methods for collecting, storing, decoding and detecting malicious codes of data packets in a window environment using 1/2 generation PT.

Optimizing LRU Lock Management in the Linux Kernel for Improving Parallel Write Throughout in Many-Core CPU Systems (매니코어 CPU 시스템의 병렬 쓰기 성능 향상을 위한 리눅스 커널의 LRU 관리 최적화 기법)

  • Eun-Kyu Byun;Gibeom Gu;Kwang-Jin Oh;Jiwoo Bang
    • KIPS Transactions on Computer and Communication Systems
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    • v.12 no.7
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    • pp.209-216
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    • 2023
  • Modern HPC systems are equipped with many-core CPUs with dozens of cores. When performing parallel I/O in such a system, there is a limit to scalability due to the problem of the LRU lock management policy of the Linux system. The study proposes an improved FinerLRU to solve this problem. Our new FinerLRU improves the parallel write performance of file systems using the buffer cache through granular lock management by increasing the number of LRU locks upto the maximum number of cores. The proposed method was implemented in Linux 5.18.11, and the performance was measured on two types of CPUs, Intel Icelake Xeon and Intel Knights landing, with different characteristics, and it was found that a performance improvement of about two times can be obtained in both types of systems.

Accelerated VPN Encryption using AES-NI (AES-NI를 이용한 VPN 암호화 가속화)

  • Jeong, Jin-Pyo;Hwang, Jun-Ho;Han, Keun-Hee;Kim, Seok-Woo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.24 no.6
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    • pp.1065-1078
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    • 2014
  • Considering the safety of the data and performance, it can be said that the performance of the AES algorithm in a symmetric key-based encryption is the best in the IPSec-based VPN. When using the AES algorithm in IPSec-based VPN even with the expensive hardware encryption card such as OCTEON Card series of Cavium Networks, the Performance of VPN works less than half of the firewall using the same hardware. In 2008, Intel announced a set of 7 AES-NI instructions in order to improve the performance of the AES algorithm on the Intel CPU. In this paper, we verify how much the performance IPSec-based VPN can be improved when using seven sets of AES-NI instruction of the Intel CPU.

디지탈시스템과 마이크로프로세서 설계 4

  • 김명항
    • 전기의세계
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    • v.31 no.10
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    • pp.710-718
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    • 1982
  • 마이크로 프로세서 구조를 설명하고 대표적인 8bit microprocessor로서 Intel의 8085를 다룬다. 또한 Microcomputer System으로 쓸 수 있는 One-Chip-Processor를 토의한다.

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해외과학기술동향

  • 김명환
    • 전기의세계
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    • v.31 no.10
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    • pp.719-727
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    • 1982
  • 마이크로 프로세서 구조를 설명하고 대표적인 8 bit microprocessor로서 Intel의 8085를 다룬다. 또한 Microcomputer System으로 쓸 수 있는 One-Chip-Processor를 토의한다.

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