• 제목/요약/키워드: input interface

검색결과 1,012건 처리시간 0.024초

A Novel Computer Human Interface to Remotely Pick up Moving Human's Voice Clearly by Integrating ]Real-time Face Tracking and Microphones Array

  • Hiroshi Mizoguchi;Takaomi Shigehara;Yoshiyasu Goto;Hidai, Ken-ichi;Taketoshi Mishima
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1998년도 제13차 학술회의논문집
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    • pp.75-80
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    • 1998
  • This paper proposes a novel computer human interface, named Virtual Wireless Microphone (VWM), which utilizes computer vision and signal processing. It integrates real-time face tracking and sound signal processing. VWM is intended to be used as a speech signal input method for human computer interaction, especially for autonomous intelligent agent that interacts with humans like as digital secretary. Utilizing VWM, the agent can clearly listen human master's voice remotely as if a wireless microphone was put just in front of the master.

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고속병렬컴퓨터(SPAX)에서의 효율적인 메시지 전달을 위한 메시지 전송 기법 (A Message Transfer Scheme for Efficient Message Passing in the Highly Parallel Computer SPAX)

  • 모상만;신상석;윤석한;임기욱
    • 전자공학회논문지B
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    • 제32B권9호
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    • pp.1162-1170
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    • 1995
  • In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

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유선 케이블 모뎀의 FEC 성능평가 (Error Performance Analysis of a FEC for the Cable Modem)

  • 이창재;김경덕;최형진
    • 한국통신학회논문지
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    • 제26권11A호
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    • pp.1803-1811
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    • 2001
  • 본 논문에서는 미국의 유선 케이블 모뎀 규격인 MCNS(Multimedia Cable Network System) DOCSIS(Data Over Cable Service Interface Specification)를 만즉하는 하향 채널의 64/256-QAM 수신부 FEC(Forward Error Correction)를 분석하였다. FEC는 기본적으로 RS(Reed-Solomon) 계층과 TCM(Trellis Coded Modulation) 계층으로 구분되며, 여기에 추가적으로 interleaving과 randomizer 계층들이 결합되어 있다. AWGN(Additive White Gaussian Noise) 환경에서의 BER(Bit Error Rate) 성능평가를 통해 수신부 연판정 비터비 복호기(soft Viterbi decoder)의 추적 깊이(trace-back depth)와 양자화 레벨(quantization level)의 크기에 따라 부호화 이득이 변함을 확인하였다.

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모의 지능로봇에서 음성신호에 의한 감정인식 (Speech Emotion Recognition by Speech Signals on a Simulated Intelligent Robot)

  • 장광동;권오욱
    • 대한음성학회:학술대회논문집
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    • 대한음성학회 2005년도 추계 학술대회 발표논문집
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    • pp.163-166
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    • 2005
  • We propose a speech emotion recognition method for natural human-robot interface. In the proposed method, emotion is classified into 6 classes: Angry, bored, happy, neutral, sad and surprised. Features for an input utterance are extracted from statistics of phonetic and prosodic information. Phonetic information includes log energy, shimmer, formant frequencies, and Teager energy; Prosodic information includes pitch, jitter, duration, and rate of speech. Finally a patten classifier based on Gaussian support vector machines decides the emotion class of the utterance. We record speech commands and dialogs uttered at 2m away from microphones in 5different directions. Experimental results show that the proposed method yields 59% classification accuracy while human classifiers give about 50%accuracy, which confirms that the proposed method achieves performance comparable to a human.

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모바일 사용자 작업 예측 모델 및 정확도 평가 기법 (Mobile User Task Prediction Models and Accuracy Evaluation Method)

  • 강영민;옥수열
    • 한국정보통신학회논문지
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    • 제11권9호
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    • pp.1742-1748
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    • 2007
  • 모바일 서비스에 대한 편리한 접근을 제공하고 휴대 장치의 활용 효율을 제고하기 위해서는 제한된 입출력 환경에서 효율적인 작업 선택과 전환 등을 보장할 수 있는 지능적인 사용자 인터페이스가 요구된다. 본 논문은 이러한 지능적 사용자 인터페이스 구현에 필수적인 사용자 작업 예측 모델을 제시하고 이러한 모델을 통한 예측의 정확도를 평가할 수 있는 기법을 제안한다.

NBLAST: a graphical user interface-based two-way BLAST software with a dot plot viewer

  • Choi, Beom-Soon;Choi, Seon Kang;Kim, Nam-Soo;Choi, Ik-Young
    • Genomics & Informatics
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    • 제20권3호
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    • pp.36.1-36.6
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    • 2022
  • BLAST, a basic bioinformatics tool for searching local sequence similarity, has been one of the most widely used bioinformatics programs since its introduction in 1990. Users generally use the web-based NCBI-BLAST program for BLAST analysis. However, users with large sequence data are often faced with a problem of upload size limitation while using the web-based BLAST program. This proves inconvenient as scientists often want to run BLAST on their own data, such as transcriptome or whole genome sequences. To overcome this issue, we developed NBLAST, a graphical user interface-based BLAST program that employs a two-way system, allowing the use of input sequences either as "query" or "target" in the BLAST analysis. NBLAST is also equipped with a dot plot viewer, thus allowing researchers to create custom database for BLAST and run a dot plot similarity analysis within a single program. It is available to access to the NBLAST with http://nbitglobal.com/nblast.

대화면 FPS 게임을 위한 레이저센서기반의 대형스크린과 레이저광원 권총의 설계와 구현 (Laser-recognizable Screen and Gun with Laser Source for Realistic Big Screen First Person Shooters Games)

  • 한녹손;김성환
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2008년도 춘계학술발표대회
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    • pp.481-484
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    • 2008
  • In this paper, we present a new game interface design for First Person Shooters (FPS). Previously, FPS on computer is commonly played using keyboard/mouse or joystick along with PC display. We improve the communication environment between player and game world by means of new control system including large screen and laser gun, which create a real life-like space for players. Because traditional display for FPS uses CRT, it cannot support large screen display due to limitation of CRT technology. We designed and implemented a new input device using laser recognizable display. Results suggest that the combined interface creates a method which helps beginners to enjoy playing a FPS immediately and gives experienced players a new gaming experience.

모니터링과 제어를 위한 사출성형 파라미터 인터페이스에 관한 연구 (A Study on the Interface of Injection Molding Parameter for Monitoring and Control)

  • 허은영;문덕희;박철순;김종민;이철수
    • 한국정밀공학회지
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    • 제31권7호
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    • pp.585-590
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    • 2014
  • Recently, monitoring systems, such as POP, take a core role in scheduling or planning of manufacturing facilities for production, maintenance, and so on. Such monitoring systems require functionalities for real-time parameter monitoring and controlling to maximize efficiency of facilities. However, vendors usually do not provide internal communication protocols or interface to access the machine controller. Therefore, the values of parameters related to machine operations and controls cannot be easily accessed from external devices. In this paper, we propose an interface methodology for a real-time monitoring and controlling of injection molding machine parameters such as user input parameters, embedded sensor data and injection molding status information.

Telescopic 증폭기를 이용한 고속 LVDS I/O 인터페이스 설계 (Design of a High-Speed LVDS I/O Interface Using Telescopic Amplifier)

  • 유관우;김정범
    • 대한전자공학회논문지SD
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    • 제44권6호
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    • pp.89-93
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    • 2007
  • 본 논문은 3.3V, $0.35{\mu}m$ CMOS 기술을 이용하여 I/O 인터페이스를 설계, 검증하였다. LVDS (low-voltage differential signaling)는 차동전송 방식과 저 전압의 스윙으로 저 전력 고속의 데이터를 전송할 수 있다. 본 논문은 기존의 차동증폭기나 감지 증폭기를 사용한 LVDS와 달리 telescopic 증폭기를 이용하여 2.3 Gbps의 빠른 전송속도를 갖는 LVDS 고속 인터페이스를 구현하였다. LVDS의 표준을 모두 충족하였고 25.5mW의 전력소모를 갖는다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

FPGA를 이용한 시퀀스 로직 제어용 고속 프로세서 설계 (The Design of High Speed Processor for a Sequence Logic Control using FPGA)

  • 양오
    • 대한전기학회논문지:전력기술부문A
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    • 제48권12호
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    • pp.1554-1563
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    • 1999
  • This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

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