• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.547-550
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• 2009

This paper presents a digital based input/output interface circuit for controlling and monitoring the Diesel Engine Generator for Emergency. In order to monitor and control of the Emergency Diesel Engine Generator, controlling and monitoring circuits need 5 analog input channels, 2 pick-up coil measuring circuits, 10 digital input channels containing Broken Wire Detect function, and 7 relay control signal output channels. This system performs signal processing of input signal taking advantage of simple filter circuit, photo-coupler and comparator circuit at analog input parts, and output signals for main relay is designed acting by double control, so it prevents malfunction completely. And it improves accuracy of speed input signal by applying digital circuit that processes pick-up coil signal.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.5
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• pp.463-470
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• 2015

In this paper, a new dual-band bandpass filter(BPF) that has resonators and feed lines with Stepped-Impedance Resonator(SIR) structures is proposed. Feed lines with SIR structure provide maximum magnetic field points which occur at the same locations of the input and output feed lines, so the insertion loss of BPF was reduced. Applying the SIR structure to the BPF for the first passband improves rejection characteristics between the first passband and the second passband. It reduces the coupling between the BPF for the first passband and the BPF for the second passband, so it makes the dual-band BPF more compact. The proposed design method provides independent changes of both the center frequency and the bandwidth for each resonator, and also improves filtering characteristics. The validity of the proposed design method is confirmed by comparisons between the designed parameters and the measured results satisfying WLAN specifications.

• Journal of Advanced Navigation Technology
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• v.9 no.2
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• pp.103-109
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• 2005

This paper presents the design of a broadband hybrid mixer using dual-gate FET topology with a low-pass filter which improves return loss of output to isolate RF and LO signal. The low-pass filter shows the isolation with RF and LO signal of better than 40 dBc from 1.5 GHz to 5.5 GHz. The dual-gate mixer which has been designed by using cascade topology operates when the lower FET is biased in linear region and the upper FET is in saturation region. The input matching circuit has been designed to have conversion gain from 1.5 GHz to 5.5 GHz. The designed mixer with low-pass filter shows the conversion gain of better than 7 dB from 1.5 GHz to 5.5 GHz at the low LO power level of 0 dBm with the fixed IF frequency of 21.4 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.132-139
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• 2016

In the bandpass sampling(BPS), the sampling frequency for the analog-to-digital converter is lower than that of the signal to be sampled. Since the BPS operation results in the signal spectrum to be copied on the baseband, it is possible for the frequency down-converter to be conveniently omitted. The second-order BPS system is introduced in order to cancel the aliased interference components from the BPS output that may be generated by the BPS processing. In this paper, we introduce a design method for the optimal phase of the interpolant filter in the second-order BPS system which enables to maximally cancel the aliased components. Being mathematically derived, this method can always be applied independently to the spectral characteristics of the BPS input signal. The performance improvements by the suggested method has been measured statistically with various power spectra of the received signal, and it has been shown that the maximal amount of the improvements reaches up to 5~20 [dB] in comparison with the previous suboptimal algorithm.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1157-1160
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• 1998

This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256$\times$256 lenna image has been simulated using IDL(Interactive Data Language). The 2-D array structured BDFA for the 2-D filter has been modeled and simulated using VHDL.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.9
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• pp.1264-1269
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• 2013

In this paper, we study a disturbance observer (DOB) based controller for an EMS(Electro-Magnetic Suspension) system in presence of mass uncertainty and input disturbance. The DOB based controller is employed in order to compensate the modeling uncertainty and attenuate disturbance signals. For the design of DOB based controller, the Jacobain linearization of nonlinear system model equation is used. Computer simulation is carried out for nonlinear model in order to compare the performance of the proposed DOB controller with that of the conventional PID controller. The simulation results show that the substantial improvement in the performance can be achieved by the proposed DOB controller.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.3
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• pp.259-265
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• 2012

This paper introduces a method for design and implementation of a current controller for boost converter operating in continuous conduction mode (CCM) using a digital signal processor (DSP). A Proportional-Integral (PI) type current controller outputs an average voltage command for inductor, used in the input side of the boost converter, and the duty-ratio of PWM (pulse width modulation) signal for switching device is directly calculated from the average voltage command. The gains of the PI current controller are selected such that the current response characteristics are the same as those of a first-order low-pass filter. The proposed current control scheme is implemented using a DSP based on fixed-point math operations and an experimental study has been performed to validate the proposed method.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.864-867
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• 2002

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. in this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtains a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.175-182
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• 2007

In this paper, a study on the reflector type frequency doubler, to suppress the undesired harmonics, is presented. A 12 to 24 GHz reflective frequency doubler is simulated and experimented. Design procedure of the frequency doubler with reflector is provided and the frequency doubler with good spectral purity is fabricated successfully. It has harmonic suppression of the $40{\sim}50\;dBc$ in the $1^{st}$ harmonic and the $50{\sim}60\;dB$ in the $3^{rd}$ harmonic with no additional filter. And, it has conversion gain with the input power of 0 dBm over bandwidth of 500 MHz. A NEC's ne71300(N) GaAs FET is used and the nonlinear model(EEFET3) using IC-CAP program is extracted for harmonic load pull simulation. Good agreement between simulated and measured results has been achieved.