• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• Journal of IKEEE
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• v.21 no.4
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• pp.353-357
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• 2017

In order to maintain numerous server systems used in enterprise and data center environments, the most important thing is to prevent the occurrence of UE (Uncorrectable Error) of each server system. With the recent development of cloud services, more memory modules are being used than ever before, while the operating frequency of server systems has increased and the process of developing memory has continued to shrink, making it more likely to fail. In these environments, there is a way to repair memory defects directly in the server system, but there is no currently available guideline to use it effectively. In this paper, we propose a method to effectively prevent memory failure in a server system based on the observation and analysis of memory failure phenomenon in existing system.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.212-224
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• 2000

In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.115-122
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• 2004

This paper describe the implementation or the boot loader for the boot system using of memory card. This boot roader consist of the system initialization, CF card checking, CF memory card checking, file system and the program relocator. This boot loader increase the system stability with program consistency checking algorithm in the read phase from the CF memory card. And this system have the compatibility in CF memory card file system, so system manufacturing productivity increase.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.596-599
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• 1997

In this study, the flow control system with shape memory alloy in jet engine inlet was suggested to adjust the shock boundary layer interact~on for supersonic flight system. It consisted of the flap with shape memory alloy, spar with steel, and fixing device with aluminum alloy. The advantages of itself are a simple configuration, a passive air circulation by using the flap deflection due to pressure difference, and no need to be required the auxiliary devices. Finite element analysis was conducted to predict the thenno-mechanical behavlor of the flap system with shape memory alloy. The user-defined subroutine UMAT was implemented with ABAQUS to accon~modate the thermo-mechanical constitutive relation of shape memory alloy.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.683-695
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• 2007

NAND flash memory-based file systems cannot store their system-related information in the file system due to wear-leveling of NAND flash memory. This forces NAND flash memory-based file systems to scan the whole flash memory during their mounts. The mount time usually increases linearly according to the size of and the usage pattern of the flash memory. NAND flash memory has been widely used as the storage medium of mobile devices. Due to the fact that mobile devices have unstable power supply, the file system for NAND flash memory requires stable recovery mechanism from power failure. In this paper, we present design and implementation of a new NAND flash memory-based file system that provides fast mount and enhanced stability. Our file system mounts 19 times faster than JFFS2's and 2 times faster than YAFFS's. The stability of our file system is also shown to be equivalent to that of JFFS2.

• ETRI Journal
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• v.44 no.3
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.694-698
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• 2004

In this paper, as one of these efforts for making the intelligent data mining system we propose the Associative frame of the memory according to the following three steps. First,the structured frame for performing the main brain function should be made. In this frame, the concepts of learning memory and episode memory are considered. Second,the learning mechanism for data acquisition and storing mechanism in the memory frame are provided. The obtained data are arranged and stored in the memory following the rules of the structured memory frame. Third, it is the last step of processing the inference and knowledge retrieval function using the stored knowledge in the associative memory frame. This system is applied to the area for estimating the purchasing degree from the type of customer's tastes, the pattern of commodities and the evaluation of a company.

• Journal of Korea Multimedia Society
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• v.19 no.7
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• pp.1179-1187
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• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• Molecules and Cells
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• v.41 no.7
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• pp.646-652
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• 2018

Neurodegeneration can result in memory loss in the central nervous system (CNS) and impairment of taste and smell in the peripheral nervous system (PNS). The neurodegeneration seen in Parkinson's disease (PD) is characterized by functional loss of dopaminergic neurons. Recent studies have also found a role for dopaminergic neurons in regulating taste memory rewards in insects. To investigate how taste memories and sugar sensitivity can be affected in PD, we utilized the $DJ-1{\beta}$ mutant fruit fly, $DJ-1{\beta}^{ex54}$, as a PD model. We performed binary choice feeding assays, electrophysiology and taste-mediated memory tests to explore the function of the $DJ-1{\beta}$ gene in terms of sugar sensitivity as well as associative taste memory. We found that PD flies exhibited an impaired ability to discriminate sucrose across a range of sugar concentrations, with normal responses at only very high concentrations of sugar. They also showed an impairment in associative taste memory. We highlight that the taste impairment and memory defect in $DJ-1{\beta}^{ex54}$ can be recovered by the expression of wild-type $DJ-1{\beta}$ gene in the dopaminergic neurons. We also emphasized the role of dopaminergic neurons in restoring taste memory function. This impaired memory property of $DJ-1{\beta}^{ex54}$ flies also allows them to be used as a model system for finding supplementary dietary foods that can improve memory function. Here we provide evidence that the associative taste memory of both control and $DJ-1{\beta}^{ex54}$ flies can be enhanced with dietary supplementation of the medicinal plant, omija.