• Journal of the Korea Convergence Society
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• v.10 no.12
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• pp.17-22
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• 2019

Network attack analysis and visualization methods using network traffic session data detect network anomalies by visualizing the sender's and receiver's IP addresses and the relationship between them. The traffic flow is a critical feature in detecting anomalies, but simply visualizing the source and destination IP addresses symmetrically from up-down or left-right would become a problematic factor for the analysis. Also, there is a risk of losing timely security situation when designing a visualization interface without considering the temporal characteristics of time-series traffic sessions. In this paper, we propose a visualization interface and analysis method that visualizes time-series traffic data by using the radial axis, divide IP addresses into network and host portions which then projects on the cylindrical coordinate system that could effectively monitor network attacks. The proposed method has the advantage of intuitively recognizing network attacks and identifying attack activity over time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.73-79
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• 2007

In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

• Journal of Internet Computing and Services
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• v.4 no.1
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• pp.53-65
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• 2003

I/O processing speed of relatively sluggish storage devices incurs overall performance degradation in computer systems. As a solution to improve the situation, SAN(Storage Area Network) has been proposed. In order to utilize a SAN system more effectively, where storage devices are directly connected with a high speed network such as Fibre Channel, a proper management tool is needed. In this paper, we present a design and implementation of a performance monitoring and configuration management tool for the SANtopia system which supports global file sharing in the SAN environment The developed tool is to monitor the performance of the Linux hosts composing the SANtopia system and to manage the configuration of the hosts and storage devices. It also supports GUI(Graphic User Interface) environment using the JAVA programming language.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.628-632
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• 2003

An intelligent miniature humanoid robot system is designed and implemented as a platform for researching walking algorithm. The robot system consists of a mechanical robot body, a control system, a sensor system, and a human interface system. The robot has 6 dofs per leg, 3 dofs per arm, and 2 dofs for a neck, so it has total of 20 dofs to have dexterous motion capability. For the control system, a supervisory controller runs on a remote host computer to plan high level robot actions based on the vision sensor data, a main controller implemented with a DSP chip generates walking trajectories for the robot to perform the commanded action, and an auxiliary controller implemented with an FPGA chip controls 20 actuators. The robot has three types of sensors. A two-axis acceleration sensor and eight force sensing resistors for acquiring information on walking status of the robot, and a color CCD camera for acquiring information on the surroundings. As an example of an intelligent robot action, some experiments on playing soccer are performed.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11S
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• pp.3410-3419
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• 1999

Autonomous Intrusion Analysis Agent(AIAA) is Incident Response Team staff's tool that scans, analyses, reports and alerts the traces of intrusion based on system logs and intruder's backdoors inside compromised system by IR staff after security incident is reported to the IR team. AIAA is intelligent to recognize to check out who is intruder from all the user accounts and to report the suspected candidates to the master control system in IR team. IR staff who controls AIAA with master system can pick up an intruder from the candidates reported by AIAA agent and review all related summary reports and details including source host's mane, finger information, all illegal behavior and so on. AIAA is moved to compromised system by the staff to investigate the signature of intrusion along the trace of victim hosts and it is also operated in secret mode to detect the further intrusion. AIAA is alive in all victim systems until the incident is closed and IR staff can control AIAA operation and dialogue with AIAA agent in Web interface.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.391-398
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• 2007

In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.

• Structural Engineering and Mechanics
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• v.34 no.4
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• pp.449-474
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• 2010

A smart hollow cylinder consisting of a host functionally graded elastic core layer and two surface homogeneous piezoelectric layers is presented in this paper. The bonding between the layers can be perfect or imperfect, depending on the parameters taken in the general linear spring-layer interface model. The effect of such weak interfaces on free vibration and steady-state response is then investigated. Piezoelectric layers at inner and outer surfaces are polarized axially or radially and act as a sensor and an actuator respectively. For a simply supported condition, the state equations with non-constant coefficients are obtained directly from the formulations of elasticity/piezoelasticity. An approximate laminated model is then introduced for the sake of solving the state equations conveniently. It is further assumed that the hollow cylinder is embedded in an elastic medium and is simultaneously filled with compressible fluid. The interaction between the structure and its surrounding media is taken into account. Numerical examples are finally given with discussions on the effect of some related parameters.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1658-1660
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• 2007

We fabricate green device having unique life time characteristics of operating voltage reduction with time, ${\Delta}V_{op}$ <0. A green device needs lower voltage than initial voltage for sustaining constant current as life time goes on. It means there are two possible reasons; one is interface modification between anode and HIL due to oxygen plasma treatment and the other is bulk property modification due to combination of new green host and new green dopant. From these materials and oxygen plasma treatment, we can make white OLED device having the characteristics of low ${\Delta}V_{op}$ increasing.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.139-147
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• 2017

In recent years, non-volatile memory express (NVMe), a new host controller interface standard, has been adapted to overcome performance bottlenecks caused by the acceleration of solid state drives (SSD). Recently, performance breakthrough cases over AHCI based SATA SSDs by adapting NVMe based PCI Express (PCIe) SSD to servers and PCs have been reported. Furthermore, replacing legacy eMMC-flash storage with NVMe based storage is also considered for next generation of mobile devices such as smartphones. The Linux kernel includes drivers for NVMe support, and as the kernel version increases, the implementation of the NVMe driver code has changed. However, mobile devices are often equipped with older versions of Android operating systems (OSes), where the newest features of NVMe drivers are not available. Therefore, different features of different NVMe driver implementations are not well evaluated on Android OSes. In this paper, we analyze the response time of the NVMe driver for various Linux kernel version.