• ETRI Journal
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• v.35 no.4
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• pp.578-586
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• 2013

Using a sub-terahertz (sub-THz) wave generated using a photonics-based technology, a high-speed wireless link operating at up to 10 Gbps is designed and demonstrated for realization of seamless connectivity between wireless and wired networks. The sub-THz region is focused upon because of the possibility to obtain sufficient bandwidth without interference with the allocated RF bands. To verify the high-speed wireless link, such dynamic characteristics as the eye diagrams and bit error rate (BER) are measured at up to 10 Gbps for non-return-to-zero pseudorandom binary sequence $2^{31}-1$ data. From the measurement results, a receiver sensitivity of -23.5 dBm at $BER=10^{-12}$ is observed without any error corrections when the link distance between the transmitter and receiver is 3 m. Consequently, we hope that our design and experiment results will be helpful in implementing a high-speed wireless link using a sub-THz wave.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.193-204
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• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• Journal of electromagnetic engineering and science
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• v.2 no.1
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• pp.39-44
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• 2002

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution because of the strict requirement far the real-time data transmission of the massive SAR data in a limited time of mission. In this paper, based on the data lint model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.3
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• pp.150-154
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• 2011

The technology to build high speed network using low cost DSL in the areas where the cost to build high speed network is high and the network environment is not very accommodating is important in providing the high speed network that meets the user demand and utilizing the network resources in an efficient way. This study presents development of the link aggregation equipment that performs the access control and firewall functions for packet processing based LAN users. The equipments developed support up to 5 line link aggregation as opposed to current 2 line link aggregation. The equipments also allow the use of high speed network in the areas where the network environment is not very accommodating. Also, the fail-over function is added to each line to provide reliability and the self-security function is enhanced to protect the network from unauthorized use and prevents waste of network resources by authorized users.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.10
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• pp.544-554
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• 1999

Multi-level inverters are now receiving widespread interest form the industrial drives for high power variable speed applications. Especially, for the high power variable speed applications, a diode clamped multi-level inverter has been widely used. However, it has the inherent problem that the voltage of the link capacitors fluctuates. This paper describes a voltage control scheme effectively to suppress the DC-link potential fluctuation for a diode clamped four-level inverter. The current to flow from/into the each link capacitor is analyzed and the operation limit is obtained when a conventional SVPWM is used. To overcome the operation limit, a modified carrier-based SVPWM is proposed. Various simulation and experiment results are presented to verify the proposed voltage control scheme for DC-link voltage balancing.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1436-1439
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• 2002

In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.558-560
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• 2019

Recently, there are steadily required more highly broadcasting service based on the broadcasting extension and improved quality. This paper proposed the method of the implemented above mentioned. The proposed high speed data link techniques method is more improved processing speed and more efficiently editing advantage compare with earlier methods.

• Journal of Advanced Navigation Technology
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• v.5 no.2
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• pp.149-157
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• 2001

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution. It is due to the strict requirement for the real-time data transmission from a series of massive raw image data of spaceborne SAR to the ground station in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.498-502
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• 2004

In a link-motion mechanism, numerous links are interconnected and each link executes a constrained motion at a high speed. Due to the complicated constrained motions of the constituent links, dynamic unbalance forces and moments are generated and transmitted to the main frame. Therefore unwanted vibration is produced. This degrades productivity and precise work. Based on constrained multi-body dynamics, the kinematic analysis is carried out to enable design changes to be made. This will provide the fundamental information for significantly reducing dynamic unbalance forces and moments which are transmitted to the main frame. In this work, a link-motion punch press is selected as an example of a link-motion mechanism. To calculate the mass and inertia properties of every link comprising a link-motion punch press, 3-dimensional CAD software is utilized. The main issue in this work is to eliminate the first-order unbalance force and moment in a link-motion punch press. The mass, moment of inertia link length, location of the mass center in each link have a great impact on the degree of dynamic balancing which can be achieved maximally. Achieving good dynamic balancing in a link motion punch press is quite essential fur reliable operation at high speed.