• Title/Summary/Keyword: hierarchical network design

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Hierarchical Cellular Network Design with Channel Allocation Using Genetic Algorithm (유전자 알고리즘을 이용한 다중계층 채널할당 셀룰러 네트워크 설계)

  • Lee, Sang-Heon;Park, Hyun-Soo
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2005.10a
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    • pp.321-333
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    • 2005
  • With the limited frequency spectrum and an increasing demand for cellular communication services, the problem of channel assignment becomes increasingly important. However, finding a conflict free channel assignment with the minimum channel span is NP hard. As demand for services has expanded in the cellular segment, sever innovations have been made in order to increase the utilization of bandwidth. The innovations are cellular concept, dynamic channel assignment and hierarchical network design. Hierarchical network design holds the public eye because of increasing demand and quality of service to mobile users. We consider the frequency assignment problem and the base station placement simultaneously. Our model takes the candidate locations emanating from this process and the cost of assigning a frequency, operating and maintaining equipment as an input. In addition, we know the avenue and demand as an assumption. We propose the network about the profit maximization. This study can apply to GSM(Global System for Mobile Communication) which has 70% portion in the world. Hierarchical network design using GA(Genetic Algorithm) is the first three-tier (Macro, Micro, Pico) model, We increase the reality through applying to EMC (Electromagnetic Compatibility Constraints). Computational experiments on 72 problem instances which have 15${\sim}$40 candidate locations demonstrate the computational viability of our procedure. The result of experiments increases the reality and covers more than 90% of the demand.

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General Purpose Operation Unit Using Modular Hierarchical Structure of Expert Network (Expert Network의 모듈형 계층구조를 이용한 범용 연산회로 설계)

  • 양정모;홍광진;조현찬;서재용;전홍태
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09b
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    • pp.122-125
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    • 2003
  • By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

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Torus Ring : Improving Performance of Interconnection Networks by Modifying Hierarchical Ring (Torus Ring : 계층 링 구조의 변형을 통한 상호 연결망의 성능 개선)

  • Kwak, Jong-Wook;Ban, Hyong-Jin;Jhon, Chu-Shik
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.5
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    • pp.196-208
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    • 2005
  • In multiprocessor systems, interconnection network design is critical for overall system performance. Popular interconnection networks, which are generally considered, are meshes, rings, and hierarchical rings. In this paper, we propose (')Torus Ring('), which is a modified version of hierarchical ring. Torus Ring has the same complexity as the hierarchical rings, but the only difference is the way it connects the local rings. It has an advantage over the hierarchical rings when the destination of a packet is the neighbor local ring in the reverse direction. Though the average number of hops in Torus Ring is equal to that of the hierarchical rings when assuming the uniform distribution of each transaction, the benefits of the number of hops are expected to be larger because of the spatial locality in the real environment of parallel programming. In the simulation results, latencies in the interconnection network are reduced by up to 19$\%$, and the execution times are reduced by up to 10$\%$.

Remote Monitoring with Hierarchical Network Architectures for Large-Scale Wind Power Farms

  • Ahmed, Mohamed A.;Song, Minho;Pan, Jae-Kyung;Kim, Young-Chon
    • Journal of Electrical Engineering and Technology
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    • v.10 no.3
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    • pp.1319-1327
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    • 2015
  • As wind power farm (WPF) installations continue to grow, monitoring and controlling large-scale WPFs presents new challenges. In this paper, a hierarchical network architecture is proposed in order to provide remote monitoring and control of large-scale WPFs. The network architecture consists of three levels, including the WPF comprised of wind turbines and meteorological towers, local control center (LCC) responsible for remote monitoring and control of wind turbines, and a central control center (CCC) that offers data collection and aggregation of many WPFs. Different scenarios are considered in order to evaluate the performance of the WPF communications network with its hierarchical architecture. The communications network within the WPF is regarded as the local area network (LAN) while the communication among the LCCs and the CCC happens through a wide area network (WAN). We develop a communications network model based on an OPNET modeler, and the network performance is evaluated with respect to the link bandwidth and the end-to-end delay measured for various applications. As a result, this work contributes to the design of communications networks for large-scale WPFs.

A Study on the Effects of Urban Public Transportation Retrofitting for Sustainability (지속가능성을 위한 도시 대중교통 레트로핏(Retrofitting) 효과분석)

  • KIM, Seunghyun;NA, Sungyoung;KIM, Jooyoung;LEE, Seungjae
    • Journal of Korean Society of Transportation
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    • v.36 no.1
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    • pp.23-37
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    • 2018
  • In recent years, it is very difficult to construct and expand new infrastructures in a city center because of long-term low growth and lack of space due to urban overcrowding. So, there is a need to study a variety of Retrofitting techniques and urban applications that can lead to sustainable development while efficiently utilizing existing facilities. 'Retrofit' means a sustainable urban retrofitting as a directed alteration of the structures, formations and systems of existing facilities to improve energy, water and waste efficiencies. In this study, we applied a hierarchical network design technique that can reflect the structural hierarchy of a city to study how to retrofit public transportation routes in Seoul. The hierarchical network design means dividing the hierarchy according to the functions of hubs and connecting different hierarchies to form a hierarchical network. As a result of comparing the application results of various retrofitting scenarios of public transport, the differences of daily PKT and PHT by about 2.6~3.2% less than before the improvement address that the convenience of passengers is increased. Therefore, it is expected that if the route planning is established according to the proposed method, it will increase the number of passengers and the operational efficiency by the improved convenience of public transit passengers.

Hierarchical Cellular Network Design with Channel Allocation (채널할당을 고려한 다중계층 셀룰러 네트워크 설계)

  • Park, Hyun-Soo;Lee, Sang-Heon
    • Journal of the military operations research society of Korea
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    • v.34 no.2
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    • pp.63-77
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    • 2008
  • With the limited frequency spectrum and an increasing demand for cellular communication services, the problem of channel assignment becomes increasingly important. However, finding a conflict free channel assignment with the minimum channel span is NP hard. The innovations are cellular concept, dynamic channel assignment and hierarchical network design. We consider the frequency assignment problem and the base station placement simultaneously. Our model takes the candidate locations emanating from this process and the cost of assigning a frequency, operating and maintaining equipment as an input. Hierarchical network design using genetic algorithm is the first three-tier (Macro, Micro, Pico) model. We increase the reality through applying to Electromagnetic Compatibility Constraints. Computational experiments on 72 problem instances which have $15{\sim}40$ candidate locations demonstrate the computational viability of our procedure. The result of experiments increases the reality and covers 90% of the demand.

Design Considerations for Hierarchical Web Caching Scheme Using iSCSI (iSCSI를 사용한 계층적 웹 캐슁 스킴의 설계)

  • 임효택
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.161-164
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    • 2003
  • The sharing of caches among Web proxies is an important technique to reduce Web Traffic and alleviate network bottlenecks. Additionally, due to emerging network technologies cooperative Web caching among proxies shows great promise to become an effective approach for reducing Web document access latencies. Nevertheless it is not widely deployed due to the overhead of existing protocols such as ICP. We propose iSCSI-based hierarchical web caching scheme which provides more improved performance than existing web caching scheme.

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Design of Hierarchical Classifier for Classifying Defects of Cold Mill Strip using Neural Networks (신경회로망을 이용한 냉연 표면흠 분류를 위한 계층적 분류기의 설계)

  • Kim, Kyoung-Min;Lyou, Kyoung;Jung, Woo-Yong;Park, Gwi-Tae;Park, Joong-Jo
    • Journal of Institute of Control, Robotics and Systems
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    • v.4 no.4
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    • pp.499-505
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    • 1998
  • In developing an automated surface inspect algorithm, we have designed a hierarchical classifier using neural network. The defects which exist on the surface of cold mill strip have a scattering or singular distribution. We have considered three major problems, that is preprocessing, feature extraction and defect classification. In preprocessing, Top-hit transform, adaptive thresholding, thinning and noise rejection are used Especially, Top-hit transform using local minimax operation diminishes the effect of bad lighting. In feature extraction, geometric, moment, co-occurrence matrix, and histogram ratio features are calculated. The histogram ratio feature is taken from the gray-level image. For defect classification, we suggest a hierarchical structure of which nodes are multilayer neural network classifiers. The proposed algorithm reduced error rate by comparing to one-stage structure.

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A Joint Topology Discovery and Routing Protocol for Self-Organizing Hierarchical Ad Hoc Networks (자율구성 계층구조 애드혹 네트워크를 위한 상호 연동방식의 토폴로지 탐색 및 라우팅 프로토콜)

  • Yang Seomin;Lee Hyukjoon
    • The KIPS Transactions:PartC
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    • v.11C no.7 s.96
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    • pp.905-916
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    • 2004
  • Self-organizing hierarchical ad hoc network (SOHAN) is a new ad-hoc network architecture designed to improve the scalability properties of conventional 'flat' ad hoc networks. This network architecture consists of three tiers of ad-hoc nodes, i.e.. access points, forwarding nodes and mobile nodes. This paper presents a topology discovery and routing protocol for the self-organization of SOHAN. We propose a cross-layer path metric based on link quality and MAC delay which plays a key role in producing an optimal cluster-based hierarchical topology with high throughput capacity. The topology discovery protocol provides the basis for routing which takes place in layer 2.5 using MAC addresses. The routing protocol is based on AODV with appropriate modifications to take advantage of the hierarchical topology and interact with the discovery protocol. Simulation results are presented which show the improved performance as well as scalability properties of SOHAN in terms of through-put capacity, end-to-end delay, packet delivery ratio and control overhead.

Design of a Multi-level VHDL Simulator (다층 레벨 VHDL 시뮬레이터의 설계)

  • 이영희;김헌철;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.10
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    • pp.67-76
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    • 1993
  • This paper presents the design and implementation of SVSIM (Sogang VHDL SIMulator), a multi-level VHDL simulator, designed for the construction of an integrated VGDL design environment. The internal model of SVSIM is the hierarchical C/DFG which is extended from C/DFG to include the network hierarchy and local/glabal control informations. Hierarchical network is not flattened for simulation, resulting in the reduction of space complexity. The predufined/user-defined types except for the record type and the predefined/user-defined attributes are supported in SVSIM. Algorithmic-level descriptions can be siumlated by the support of recursive procedure/function calls. Input stimuli can be generated by command script in stimuli file or in VHDL source code. Experimential results show SVSIM can be efficiently used for the simulation of the pure behavioral descriptions, structural descriptions or mixture of these.

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