• Title/Summary/Keyword: harmonics rejection

Search Result 26, Processing Time 0.027 seconds

Low Phase Noise VCO Using Spiral Resonator (Spiral 공진기를 이용한 저위상 잡음 전압 제어 발진기)

  • Jwa, Dong-Woo;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.45 no.7
    • /
    • pp.77-80
    • /
    • 2008
  • In this paper, low phase noise VCO using novel compact microstrip spiral resonator is proposed. A spiral resonator has super compact dimension, low insertion losses in the passband and high level of rejection in the stopband with sharp cutoff and a large coupling coefficient value, which makes a high Q value, and has reduced the phase noise. To increase the tuning range of VCO, varactor diode has been connected at the tunable negative resistance in VCO. This VCO has presented the oscillation frequency of $5.686{\sim}5.841GHz$, harmonics -29.83 dBc and phase noise of $-115.16{\sim}-115.17dBc/Hz$ at the offset frequency of 100 KHz.

A Novel Input and Output Harmonic Elimination Technique for the Single-Phase PV Inverter Systems with Maximum Power Point Tracking (최대출력추종 제어를 포함한 단상 태양광 인버터를 위한 새로운 입출력 고조파 제거법)

  • Amin, Saghir;Ashraf, Muhammad Noman;Choi, Woojin
    • Proceedings of the KIPE Conference
    • /
    • 2019.07a
    • /
    • pp.207-209
    • /
    • 2019
  • This paper proposes a grid-tied photovoltaic (PV) system, consisting of Voltage-fed dual-active-bridge (DAB) dc-dc converter with single phase inverter. The proposed converter allows a small dc-link capacitor, so that system reliability can be improved by replacing electrolytic capacitors with film capacitors. The double line frequency free maximum power point tracking (MPPT) is also realized in the proposed converter by using Ripple Correlation method. First of all, to eliminate the double line frequency ripple which influence the reduction of DC source capacitance, control is developed. Then, a designing of Current control in DQ frame is analyzed and to fulfill the international harmonics standards such as IEEE 519 and P1547, $3^{rd}$ harmonic in the grid is directly compensated by the feedforward terms generated by the PR controller with the grid current in stationary frame to achieve desire Total Harmonic Distortion (THD). 5-kW PV converter and inverter module with a small dc-link film capacitor was built in the laboratory with the proposed control and MPPT algorithm. Experimental results are given to validate the converter performance.

  • PDF

Improved Power Performances of the Size-Reduced Amplifiers using Defected Ground Structure (결함 접지 구조를 이용하여 소형화한 증폭기의 개선된 전력 성능)

  • Lim, Jong-Sik;Jeong, Yong-Chae;Han, Jae-Hee;Lee, Young-Taek;Park, Jun-Seok;Ahn, Dal;Nam, Sang-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.13 no.8
    • /
    • pp.754-763
    • /
    • 2002
  • This paper discusses the improved power performances of the size-reduced amplifier using defected ground structure (DGS). The slow-wave effect and enlarged electrical length occur due to the additional equivalent circuit elements of DGS. Using these properties, it is possible to reduce the length of transmission lines in order to keep the same original electrical lengths by inserting DGS on the ground plane. The matching and performances of the amplifier are preserved even after DGS patterns have been inserted. While there is no loss in the size-reduced transmission lines at the operating frequency, but there exists loss to some extent at harmonic frequencies. This leads to the more excellent inherent capability of harmonic rejection of the size-reduced amplifier. Therefore, it is expected tile harmonics of the size-reduced amplifier are smaller than those of the original amplifier. The measured second harmonic, third order intermodulation distortion (IMD3), and adjacent channel power ratio (ACPR) of the size-reduced amplifier are smaller than those of the original amplifier by 5 dB, 2~6 dB, and 1~4 dB, respectively, as expectation.

Microstrip Bandpass Filter for Spurious Resonant Mode Rejection using Metameterial Transmission Line (메타매질 전송선로를 이용한 불요 공진모드 제거용 마이크로스트립 대역통과 필터)

  • Yang, Doo-Yeong;Lee, Min-Soo
    • The Journal of the Korea Contents Association
    • /
    • v.9 no.12
    • /
    • pp.566-571
    • /
    • 2009
  • In this paper, microstrip bandpass filter combined DCRLH metameterial-cells with a hairpin resonator is designed and fabricated to be transferred only fundamental passband signal, and removed a spurious resonant mode occurring when filter design using a microstrip transmission line is done. The bandpass filter is composed of CCRLH hairpin resonator and DCRLH interdigit metameterial-cells. The hairpin resonator with CCRLH property is implemented between two DCRLH interdigit metameterial-cells with DCRLH property, which is parallel to input port and output port. The interdigit metameterial-cells suppress spurious harmonics occurring on the higher order frequency and improve a filter performance. Insertion loss of the fabricated microstrip bandpass filter on the passband from 1.91GHz to 2.41GHz is 0.2dB, and attenuation on the stopband from 3GHz to 7.7GHz is bellower than -30dB. Therefore, this filter has a good performance for both mobile communications of WCDMA and wireless internet of WiBro.

Output Noise Reduction Technique Based on Frequency Hopping in a DC-DC Converter for BLE Applications

  • Park, Ju-Hyun;Kim, Sung Jin;Lee, Joo Young;Park, Sang Hyeon;Lee, Ju Ri;Kim, Sang Yun;Kim, Hong Jin;Lee, Kang-Yoon
    • IEIE Transactions on Smart Processing and Computing
    • /
    • v.4 no.5
    • /
    • pp.371-378
    • /
    • 2015
  • In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

Performance Evaluations of Four MAF-Based PLL Algorithms for Grid-Synchronization of Three-Phase Grid-Connected PWM Inverters and DGs

  • Han, Yang;Luo, Mingyu;Chen, Changqing;Jiang, Aiting;Zhao, Xin;Guerrero, Josep M.
    • Journal of Power Electronics
    • /
    • v.16 no.5
    • /
    • pp.1904-1917
    • /
    • 2016
  • The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAF-based PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.