• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.46-50
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• 2013

A modified design that can reject the nth harmonic components in the Wilkinson power divider is presented. After adding transmission lines of electrical lengths determined by suppression terms between two transformers of the traditional design, a solution of the modified Wilkinson divider can be found. Experimental results show the second and third harmonic suppression to be -45.3 dB and -46.4 dB, respectively, while maintaining the conventional performance at the fundamental frequency.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.6
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• pp.217-225
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• 1986

This paper describes the Optimal PWM strategy to reduce a pulsating harmonic torque for a variable-speed drive of 3 phase induction motor. This paper suggests the new Optimal control theory which consists of 1) defining a performance index related to the unwanted effects of the voltage harmonics, (i.e., the components of pulsating harmonic torques) 2) achieving its minimization by a suitable choice of the switching patterns. (i.e., of the commutation angles) This PWM strategy is compared with the conventional SPWM strategy by numerical method. It is believed that this proposed strategy can reduce more harmonic components and pulsating harmonic torques than SPWM strategy. Also, We could verify the validety of the numerical method by a result of simulation analysis of a variable speed 3phase induction motor.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.74-78
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• 2000

In this paper a switching control circuit for shaping the line current and reducing the total harmonics distortion in the boost converter is presented. To solve the problems of performance degradation due to pulse waveform in the input current, the boost converter in which the harmonic distortion in the input current is reduced using a 3th harmonic-injected PWM is proposed. Finally, Simulation and experimental results of boost converter with 5[kHz] switching frequency are presented and correction of power factor and reduction of total harmonic distortion was established.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Speech Sciences
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• v.11 no.2
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• pp.259-269
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• 2004

In this paper, we propose a new excitation enhancement technique to improve the speech quality of low bit-rate code-excited linear prediction (CELP) coders. The proposed technique is based on a harmonic model and it is employed only in the decoding process of speech coders without any additional bits. We develop the procedure of harmonic model parameter estimation and harmonic generation, and apply this technique to a current state-of-the-art low bit rate speech coder, ITU-T G.729 Annex D. Also, its performance is measured by using the ITU-T P.862 PESQ score and compared to those of the phase dispersion filter and the long-term postfilter applied to the decoded excitation. It is shown that the proposed excitation enhancement technique can improve the quality of decoded speech and provide better quality for male speech than other techniques.

• Journal of Power Electronics
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• v.16 no.3
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• pp.960-969
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• 2016

High-power three-level voltage-source converters are widely utilized in high-performance AC drive systems. In several ultra-power instances, the harmonics on the grid side should be reduced through multiple rectifications. A combined harmonic elimination method that includes a dual primary-side series-connected winding transformer and selective harmonic elimination pulse-width modulation is proposed to eliminate low-order current harmonics on the primary and secondary sides of transformers. Through an analysis of the harmonic influence caused by dead time and DC magnetic bias, a synthetic compensation control strategy is presented to minimize the grid-side harmonics in the dual primary side series-connected winding transformer application. Both simulation and experimental results demonstrate that the proposed control strategy can significantly reduce the converter input current harmonics and eliminates the DC magnetic bias in the transformer.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.249-253
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• 2006

Because of the high cost for the active power filter, passive filters have been widly used to absorb harmonic currents of nonlinear loads and can also improve the power factor. They are not often optimal filters because the passive filters are designed with the fixed load conditions. In this paper we proposed the method which only the necessary harmonic filters are operated by detecting the various harmonic current components. By the experimental results using the proposed system for the 500VA rectifier load, we concluded that the researched hybrid filter is cost effective and the performance is better than the passive filter.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1553-1562
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• 2017

For the purpose of enhancing the performance of the shunt active power filter (APF), this paper presents a novel Fast Weighted Compound Control (FWCC) strategy based on the synchronous frame. In this control strategy, the proposed new repetitive controller can work faster and more stably by reducing the internal model cycle and introducing a damping coefficient. In addition, the harmonic detector can be removed to simplify the structure of the APF owing to the improvements. Furthermore, a proportional-integral (PI) controller is added to work in parallel with the repetitive controller by using a weighted ratio. Then, a convergence speed analysis and design algorithm are given in detail. Simulation and experimental results show that the harmonic distortion is reduced from 2.91% to 1.89%. In addition, the content for each of the characteristic harmonic orders has decreased by more than three times.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1575-1581
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• 2019

Due to the mismatched line impedance among distributed generation units (DGs) and uncontrolled harmonic current, the droop controller has a number of problems such as inaccurate reactive power sharing and voltage distortion at the point of common coupling (PCC). To solve these problems, this paper proposes a resistive-capacitive virtual impedance control method. The proposed control method modifies the DG output impedance at the fundamental and harmonic frequencies to compensate the mismatched line impedance among DGs and to regulate the harmonic current. Finally, reactive power sharing is accurately achieved, and the PCC voltage distortion is compensated. In addition, adaptively controlling the virtual impedance guarantees compensation performance in spite of load changes. The effectiveness of the proposed control method was verified by experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.30-40
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• 2015

For a shunt power quality controller (SPQC) the DC side voltage value which is closely related to the compensation performance is a significant parameter. Buy so far, very little discussion has been conducted on this in a quantitative manner by previous publications. In this paper, a method to design the DC side voltage of SPQC is presented according to the compensation performance in the single-phase system and the three-phase system respectively. First, for the reactive current and the harmonic current compensation, a required minimal value of the DC side voltage with a zero total harmonic distortion (THD) of the source current and a unit power factor is obtained for a typical load, through the equivalent circuit analysis and the Fourier Transform analytical expressions. Second, when the DC side voltage of SPQC is lower than the above-obtained minimal value, the quantitative relationship between the DC side voltage and the THD after compensation is also elaborated using the curve diagram. Hardware experimental results verify the design method.