• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8B
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• pp.541-548
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• 2005

IP lookup and forwarding process becomes the bottleneck of packet transmission as IP traffic increases. Previous hardware-based IP address lookup schemes using an index-based table are not memory-efficient due to sparse distribution of the routing prefixes. In this paper, we propose memory-efficient hardware based IP lookup scheme called set-associative IP address lookup scheme, which provides the same IP lookup speed with much smaller memory requirement. In the proposed scheme, an NHA entry stores the prefix and next hop together. The IP lookup procedure compares a destination IP address with eight entries in a corresponding set simultaneously and finds the longest matched prefix. The memory requirement of the proposed scheme is about $42\%$ of that of Lin's scheme. Thus, the set-associative IP address lookup scheme is a memory-efficient hardware based IP address lookup scheme.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.75-81
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• 2004

AE-CORDIC improves the CORDIC operation speed with a rotation direction pre-computation algorithm. Its CORDIC iteration stages consist of non-predictable rotation direction states and predictable rotation stages. The non-predictable stages are replaced with lookup-table which has smaller hardware size than CORDIC iteration stages. The predictable stages can determine rotation direction with the input angle and simple encoder. In this paper, a rotation direction pre-computation algorithm with input angle encoder is proposed. and AE-CORDIC which have optimized Lookup-table is compared with the P-CORDIC algorithm. Hardware size, delay, and SQNR of the AE-CORDIC are verified with Samsung 0.18㎛ technology and Synopsys design compiler when input angle bit length is 16.

• Journal of Communications and Networks
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• v.3 no.4
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• pp.374-382
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• 2001

Nowadays, the commonly used table lookup scheme for IP routing is based on the sc-called classless interdomain routing (CIDR). With CIDR, routers must find out the best matching prefix (BMP) for IP packets forwarding, this complicates the IP lookup. Currently, this process is mainly performed in software and several schemes hale been proposed for hardware implementation. Since the IP lookup performance is a major design issue for the new generation routers, in this article we investigate the properties of the routing table and present a new approach for IP lookups, our approach is not based Gn BMP and significantly reduces the complexity, thus the computation cast of existing schemes can be significantly reduced. We also propose an efficient IP lookup algorithm, with which we improve the binary search on prefixes to 30 millions of packets per second (MPPS) and 5,000 route updates/s under the same experiment setup with an even larger routing table.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.533-536
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• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.298-305
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• 2003

In this paper, we proposed a high performance lookup controller for IP packet forwarding engine of ATM based label edge routers. The lookup controller is designed to provide services such as MPLS, VPN, ELL, and RT services as well as the best effort. For high speed searching for IP addresses, we employed a TCAM based hardware search device not using traditional algorithmic approaches. We also implement lookup control functions into FPGA for fast processing of packet header and lookup control. The proposed lookup controller is designed to support differenciated services for users and to process in pipelined mechanism for performance improvement. A two-step search scheme is also applied to perform lookup for the key combined with multi-field of packet header. We found that the proposed lookup controller provides the performance of about 16M packets per second through simulations.

• Transactions of the Korean Society of Automotive Engineers
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• v.24 no.1
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• pp.112-121
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• 2016

AFLS (Adaptive front lighting system) is being applied to improve safety in driving automotive at night. Safe embedded system design for controlling head-lamps is required to improve noise robust ECU hardware and software simultaneously by considering safety requirement of hardware-dependent software under severe environmental noise. In this paper, we propose an adaptive headlight controller with a newly-designed symmetric angle sensor compensator, especially based on the proposed steering-swivel angle lookup table to determine whether the current controlling target is safe. The proposed system includes an additional backup hardware to compare the system status and provides safe swivel-angle management using a controlling algorithm based on the pre-defined lookup table (LUT), which is a symmetric mapping relationship between the requested steering angle and expected swivel angle target. The implemented system model shows that the proposed architecture effectively detects abnormal situations and restores safe status of controlling the light-angle in AFLS operations under severe noisy environment.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.1
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• pp.88-95
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• 2009

This paper presents a traffic pattern matching hardware that can be used in high performance network applications. The presented hardware is designed for a contents security system which is to block various kinds of information drain or intrusion activities. The hardware consists of two parts: the header lookup and string pattern matching parts. For implementing the header lookup part in hardware, the TCAMs(ternary CAMs) are popularly used. Since the TCAM approach is inefficient in terms of the hardware and memory costs and the power consumption, however, we adopt and modify an alternative approach based on the comparator arrays and the HiCuts tree. Our implementation results, using Xilinx FPGA XC4VSX55, show that our design can reduce the usage of the FPGA slices by about 26%, and the Block RAM by about 58%. In the design of string pattern matching part, we design and use a hashing module based on cellular automata, which is hardware efficient and consumes less power by adaptively changing its configuration to reduce the collision rates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3B
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• pp.65-71
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• 2005

The primary function of the Internet routers is to forward incoming packets toward their final destinations. IP address lookup is one of the most important functions in evaluating router performance since IP address lookup should be performed in wire-speed for the hundred-millions of incoming packets per second. With CIDR, the IP prefixes of routing table have arbitrary lengths, and hence address lookup by exact match is no longer valid. As a result, when packets arrive, routers compare the destination IP addresses of input packets with all prefixes in its routing table and determine the most specific entry among matching entries, and this is called the longest prefix matching. In this paper, based on parallel multiple hashing and prefix grouping, we have proposed a hardware architecture which performs an address lookup with a single memory access.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.