• 한국철도학회:학술대회논문집
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• 한국철도학회 2003년도 춘계학술대회 논문집
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• pp.450-455
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• 2003

This paper is to discuss the hardware redundancy architecture of fault-tolerance system with using redundancy. Each architecture will be studied to implement fault-tolerance in classifying hardware redundancy architecture as passive, active and hybrid hardware redundancy. Therefore Fault-Masking and Fault-Detecting Techniques in each redundancy architecture is studied.

• 전기학회논문지
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• 제63권8호
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.111-111
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• 2000

The research of network system, being used to reduce automotive wiring harness, is reaching to the development of by-wire system. It is by-wire system that apply IVN(In-Vehicle-Network) to steering, braking system, and it has the advantage of mass-decreasing, easy to diagnose fault and so on. But until now, many developed device can't satisfied with reliability that system have ever had. So redundancy of each network module, i.e., It is only way to make backup module. This paper researches development of network module and redundancy management of backup module when error occurred for implementation of brake-by-wire system.

• ETRI Journal
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• 제31권3호
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.209-210
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability.

• 대한전자공학회논문지SD
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• 제48권8호
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• pp.18-24
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• 2011

칩의 적층 기술이 적용된 TSV기반 3D IC로 진화함에 따라 새로운 문제점이 발생하게 되었다. Bonding 이후 다이간 TSV가 제대로 연결되었는지 테스트하지만 Redundnacy TSV에 대해서는 테스트하지 않는다. 그러나 더 높은 수율을 얻기 위해서는 redundancy TSV에 대한 연결 테스트를 수행해야 한다. redundancy TSV의 연결을 테스트하고 진단하여 고장 있는 TSV를 대체함으로써 더 높은 수율을 얻을 수 있다. 본 논문에서는 TSV기반 3D IC에서 다이간의 TSV 연결 테스트뿐 아니라 redundancy TSV 테스트를 위한 래퍼셀을 제안하고자 한다. 제안하는 래퍼셀은 하드웨어로 설계하였을 시 기존의 테스트패턴을 그대로 사용할 수 있고, 소프트웨어 설계 시에는 면적을 최소화할 수 있다.

• 전기학회논문지
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• 제63권12호
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• pp.1640-1648
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• 2014

This paper proposes a switching frequency reduction method for MMC (Modular Multilevel Converter) utilizing redundancy operation of sub-module, which can offer reduction of voltage harmonics and switching loss. The feasibility of proposed method was verified through computer simulations with PSCAD/EMTDC software. Based on simulation analysis, a hardware scaled-model of 10kVA, DC-1000V MMC was designed and manufactured in the lab. Various experiments were conducted to verify the feasibility of proposed method in the actual hardware system. The hardware scaled-model can be effectively utilized for analyzing the performance of MMC according to the modulation scheme and redundancy operation.

• 제어로봇시스템학회논문지
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• 제11권3호
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• pp.200-206
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• 2005

In this paper, a redundancy management system for aircraft is studied, and FDI (Fault Detection and Isolation) algorithm of inertial sensor system is proposed. UAV system cannot allow triple or quadruple hardware redundancy due to the limitations on space and weight. In the UAV system with dual sensors, it is very difficult to identify the faulty sensor. Also, conventional FDI method cannot isolate multiple faults in a triple redundancy system. In this paper, hardware based FDI technique is proposed, which combines a parity equation approach with the wavelet based technique, which is a model-free FDI method. To verify the effectiveness of the proposed FDI method, numerical simulations are performed.

• International Journal of Aeronautical and Space Sciences
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• 제7권1호
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• pp.73-83
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• 2006

In this paper, a redundancy management system for aircraft is studied, and fault detection and isolation algorithms of inertial sensor system are proposed. Contrary to the conventional aircraft systems, UAV system cannot allow triple or quadruple hardware redundancy due to the limitations on space and weight. In the UAV system with dual sensors, it is very difficult to identify the faulty sensor. Also, conventional fault detection and isolation (FDI) method cannot isolate multiple faults in a triple redundancy system. In this paper, two FDI techniques are proposed. First, hardware based FDI technique is proposed, which combines a parity equation approach with a wavelet based technique. Second, analytic FDI technique based on the Kalman filter is proposed, which is a model-based FDI method utilizing the threshold value and the confirmation time. To provide the reference value for detecting the fault, residuals are calculated using the extended Kalman filter. To verify the effectiveness of the proposed FDI methods, numerical simulations are performed.

• 한국통신학회논문지
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• 제17권11호
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• pp.1279-1289
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• 1992

고장 방지 시스템은 하드웨어나 소프트웨어의 여분 (Redundancy)을 이용하여 신뢰도(Reliability) 및 안전도(Safety)를 향상 시킨다. 시스템의 대상 영역(application areas)에 따라 고장 마스크(fault mask), 고장검출(fault detection), 고장 확인(fault identification)등의 기법을 선택하여 이용한다. 본 연구에서는 최소의 하드웨어와 소프트웨어의 여분을 이용하는 DMR(Double Modular Redundancy) 시스템을 대기 모듈(standby module)과 Fail-safe 모듈로 동작 시킬때 신뢰도와 안전도의 특성을 비교 제시한다. 또한 자기 진단 프로그램의 과도 오류 방지 능력에 대한 시스템의 MTTF를 비교함으로서 과도 오류를 취급하는 효과적인 방법을 제시하였다.