• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1213-1216
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• 2005

In this paper, we suggested the integer linear programming (ILP) models that went through constraint scheduling to simple cycle operation during the delay time. The delayed scheduling can determine a schedule with a near-optimal number of control steps for given fixed hardware constraints. In this paper, the resource-constrained problem is addressed, for the DFG optimization for multiprocessor design problem, formulating ILP solution available to provide optimal solution. The results show that the scheduling method is able to find good quality schedules in reasonable time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.2
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• pp.932-945
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• 2018

Everything in the world is becoming connected and interactive due to the Internet. The future of interactive smart environments such as smart cities, smart industries, or smart farms demand high network bandwidth, high network flexibility, and self-organization systems without costly hardware upgrades, and they provide a sustainable, scalable, and replicable smart environment backbone infrastructure. This paper presents a new Hybrid Software-Defined architecture for integrating Internet-of-Things technologies that are essential technologies for smart environments. It combines a software-defined networking infrastructure and a real-time distributed network framework with an advanced optimization to enable self-configuration, self-management, and self-adaption for providing seamless communication and efficiently managing a vast number of smart heterogeneous devices.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• International Journal of Automotive Technology
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• v.7 no.7
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• pp.841-846
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• 2006

This paper presents a numerical approach to optimizing vehicle fuel economy in a higway bus. The method described is based on using a commercial software vehicle simulation to identify the relative efficiency of each of the vehicle systems, such as the engine hardware, engine software calibration, transmission, cooling system and ancillary drives. The simulation-based approach offers a detailed understanding of which vehicle systems are underperforming and by how much the vehicle fuel economy can be improved if those systems are brought up to best-in-class performance. In this way, the optimum vehicle fuel economy can be provided to the vehicle customer. A further benefit is that the simulation requires only a minimum number of vehicle testing for initial validation, with all subsequent field test cycles performed in software, thereby reducing development time and cost for the manufacturer.

• Communications for Statistical Applications and Methods
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• v.12 no.3
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• pp.697-704
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• 2005

Computer software has gradually become an indispensable elements in many aspects of our daily lives and an important factor in numerous systems. In recent years, it is not unusual that the software cost is more than the hardware cost in many situations. In addition to the costs of developing software, the repair cost resulting from the software failures are even more significant. In this paper, a cost model with warranty cost, time to remove each fault detected in the software system, and delivery delay cost is developed. We use a software reliability model based on non-homogeneous Poisson process (NHPP). We discuss the optimal release policies to minimize the expected total software cost. Numerical examples are provided to illustrate the results.

• Journal of the Korean Magnetic Resonance Society
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• v.18 no.2
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• pp.47-51
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• 2014

Larger proteins (above molecular weight 50 kDa) usually show slow motional tumbling in solution, which facilitates the decay of NMR signal, resulting in poor signal-to-noise. In the past twenty years, researchers have tried to overcome this problem with higher molecular weight by improvement of hardware (higher magnetic field and cryoprobe), optimization of pulse sequences for lager molecules, and development of isotope-labeling techniques. Actually, GroEL/ES complex (${\approx}$ 900 kDa) was successfully studied using combination of above techniques. Among the techniques used in large molecular studies, the impact of isotope-labeling for large molecules study is summarized and discussed here.

• Journal of Power Electronics
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• v.14 no.2
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.224-226
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• 2010

컴퓨터 생성 홀로그램(computer-generated hologram, CGH) 기법은 광학 신호들을 근사화한 후 PC에서 수학적인 연산으로 디지털 홀로그램을 생성하는 기술이다. 본 논문에서는 CGH 기법을 하드웨어로 구현할 경우 완벽한 병렬처리와 파이프라이닝이 가능하도록 연산식을 최적화하는 방법을 제안한다. 제안한 방법은 홀로그램의 이전 좌표에서 계산된 값에 일정한 값을 더하여 홀로그램을 생성하는 반복가산 기법의 일반항을 분석하여 하드웨어에 최적화된 수식으로 변형하는 것이다. 최적화된 수식의 경우 현재 좌표의 홀로그램을 계산하기 위해 이전 좌표에서 연산되었던 결과값을 기다렸다 이용하지 않기 때문에 실시간 디지털 홀로그래피를 위한 전용 하드웨어의 설계에 적합할 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1B
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• pp.34-41
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• 2002

In this paper, the algorithms increase the capacity of the forward link channel are studied in the DS-CDMA mobile communication system with the technology of transmit antenna array. Through of the implementation of the test bed with PC and DSP boards, the hardware implementation and optimization of the algorithms, the operation scenario and architecture of the test bed, are considered. In addition, the performance analyses are achieved about the execution time of the algorithms.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.34-39
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• 2001

The median barrier is one of the roadside hardware to prevent severe human and property damage from highway traffic accidents. The foreign standard of concrete median barrier was introduced and implemented without modification fitting to domestic vehicle and highway condition. In a car accident, median barrier doesn't protect vehicle effectively, especially for heavy vehicle such as bus and heavy truck. The purpose of this study is to develop the optimal performance design of concrete median barrier using the design of experiment with crash simulation analysis which is done by Pam-Crash that is one of the commercial crash simulation software. As a result of this study, an optimal design of concrete median barrier is obtained considering von Mises stress, volume and COG acceleration of truck.