• Title/Summary/Keyword: hardware fault detection

Search Result 76, Processing Time 0.022 seconds

Development of Hardware Design Process Enhancement Tool for Flight Control Computer using Modeling and Simulation (M&S 기반의 비행조종컴퓨터 하드웨어 설계 프로세스 개선을 위한 툴 개발)

  • Kwon, Jong-Kwang;Ahn, Jong-Min;Ko, Joon-Soo;Seung, Dae-Beom;Kim, Whan-Woo
    • Journal of the Korean Society for Aeronautical & Space Sciences
    • /
    • v.35 no.11
    • /
    • pp.1036-1042
    • /
    • 2007
  • It is rather difficult to improve flight control computer(FLCC) hardware(H/W) development schedule due to lack of commercial off-the-self(COTS) tools or target specific tools. Thus, it is suggested to develop an enhanced process utilizing modeling, simulation and virtual reality tools. This paper presents H/W design process enhancement tool(PET) for FLCC design requirements such as FLCC input/output(I/O) signal flow, I/O fault detection, failure management algorithm, circuit logic, PCB assembly configuration and installation utilizing simulation and visualization in virtual space. New tool will provide simulation capability of various FLCC design configuration including shop replaceable unit(SRU) level assembly/dis-assembly utilizing open flight format 3-D modeling data.

An Efficient Built-in Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories

  • Kang, Dong-Chual;Park, Sung-Min;Cho, Sang-Bock
    • ETRI Journal
    • /
    • v.26 no.6
    • /
    • pp.520-534
    • /
    • 2004
  • As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

  • PDF

Frequency-Time Analysis(Partition-FFT) for Tracking Detection (트래킹 검출을 위한 주파수-시간 분석(분할-FFT))

  • Jee S. W.;Lee S. H.;Kim Ch. N.;Lee C. H.;Lee K. S.
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.53 no.10
    • /
    • pp.530-538
    • /
    • 2004
  • A electromagnetic waves are used for sensing in insulation diagnosis at electric machine or equipment. When it a method, waves are transformed into the FFT(Fast Fourier Transform); a kind of the process for data transformation. In a general way, a scientist use frequncy band 30[㎒]~l[㎓] to applied field. If we are measured high frequency band, we will need to a high capacity hardware. Also a antenna has a fault on atmospheric phenomena, outside environment and the like. In this paper We proposed new method for detecting electric equipment faulty state using only electric voltage which is generally measured in the electric and electronic field. It is called the Partition-FFT The analytic method is this first divide measured voltage waves into equal parts, second each deal with give effect to the FFT, finally each results deal with a graphic method and gather graphic. We are compare Partition-FFT with discharge form by tracking tester. As the result it demonstrated that the Partition-FFT is applicable.

Design and development of enhanced criticality alarm system for nuclear applications

  • Srinivas Reddy, Padi;Kumar, R. Amudhu Ramesh;Mathews, M. Geo;Amarendra, G.
    • Nuclear Engineering and Technology
    • /
    • v.50 no.5
    • /
    • pp.690-697
    • /
    • 2018
  • Criticality alarm systems (CASs) are mandatory in nuclear plants for prompt alarm in the event of any criticality incident. False criticality alarms are not desirable as they create a panic environment for radiation workers. The present article describes the design enhancement of the CAS at each stage and provides maximum availability, preventing false criticality alarms. The failure mode and effect analysis are carried out on each element of a CAS. Based on the analysis, additional hardware circuits are developed for early fault detection. Two different methods are developed, one method for channel loop functionality test and another method for dose alarm test using electronic transient pulse. The design enhancement made for the external systems that are integrated with a CAS includes the power supply, criticality evacuation hooter circuit, radiation data acquisition system along with selection of different soft alarm set points, and centralized electronic test facility. The CAS incorporating all improvements are assembled, installed, tested, and validated along with rigorous surveillance procedures in a nuclear plant for a period of 18,000 h.

Real-Time Object Model dRTO (실시간 객체 모델 dRTO)

  • Lee, Sheen;Son, Hyuk-Su;Yang, Seung-Min
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.27 no.3
    • /
    • pp.300-312
    • /
    • 2000
  • The application areas of embedded real-time systems are very wide and so are the requirements for real-time processing and reliability of the systems. To develop embedded real-time systems effectively with its real-time and reliability properties guaranteed, an appropriate real-time model is needed. Recently, the research on real-time object-oriented model is active, which graft the concept of object-orientation on real-time systems modeling and development. In this paper, we propose dRTO (dependable Real-Time Object) model, with 5 primitive classes. These allow designers to effectively model the characteristics of real-time systems, i.e., object-orientation, real-time-ness and dependability. The dRTO model has three main features. First, it is able to model and implement the timing constraints imposed on real-time objects as well as interactions among the objects. Second, hardware and software components (including kernel) of embedded systems can be modeled in one frame. Third, it is able to represent fault detection and recovery mechanisms explicitly.

  • PDF

Implementation of Incoming Panel Monitoring System using Open Source Platform and Wi-Fi Networks (오픈소스 플랫폼 및 Wi-Fi를 이용한 수배전반 모니터링 시스템 구현)

  • Kang, Jin-Young;Kang, Hag-Seong;Jeong, Sung-Hak;Park, Mi-Young;Lee, Young-Dong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2015.05a
    • /
    • pp.886-887
    • /
    • 2015
  • There is a growing interest in and demand for power industry acceleration and energy efficiency due to the increased energy consumption, environmental issues. Electronic power IT convergence industries such as intelligent power system has attract attention as new growth engine industry. A large number of sensors and motors are being installed following unmanned, automated in existing incoming panel management system. Observe the operating conditions and rapid response is essential. Despite the need for immediate action to be taken in the event of various later failed to recognize the emergency power can lead to accidents. In this paper, we propose a new architecture of the implementation of incoming panel monitoring system for power monitoring, fault detection, maintenance and system control using open source hardware platform and Wi-Fi networks.

  • PDF