• Communications of the Korean Institute of Information Scientists and Engineers
• /
• v.4 no.2
• /
• pp.95-103
• /
• 1986

Computer는 발명되서부터 매년 응용분야가 넓어지고 있다. 현재에는 情 報處理라는 말그대로 어떠한 형태이든가의 복잡하고 다량의 情報가 存在하는 곳 에는 computer를 導入할려고 하든가, 또는 導入이 끝난 곳에서는 보다 큰 大規模 의 system으로 擴張하려고 하는 생각들을 보통 가지고 있다. 이러한 요구에 응하 여 왔던 것이 hardware, oprating system, 그리고 application software이다. 그중 hardware나 operating system은 多小 變化하여 왔지만은, 方式的으로는 application의 특성에 의한 요구에는 별로 틀린것이 없이 대개 같은 종류의 것이 쓰여왔다고 할 수 있다. 따라서 무수히 變하는 application의 複雜한 論理를 實現 하는 것은, 그 책임이 application software 개발자에 걸려있다. 그러므로 이러한 것들은 개발자(designer, programmer) 들의 개인의 기술과 努力에 달렸다고 말할 수 있다.

• The KIPS Transactions:PartA
• /
• v.11A no.5
• /
• pp.303-312
• /
• 2004

In this paper, we propose a methodology solving the problem of the hardware-software partitioning in reconfigurable systems using a Y-chart design space exploration and implement a simulator according to the methodology. The methodology generates a mapping set between tasks and hardware elements using the hardware element model and the application model. We evaluate the throughput by simulating cases in each mapping set. With the throughput evaluation result, we can select the mapping case with the highest throughput. We also propose an heuristic improving the simulation time by reducing the mapping set on the basis of the relationship between workload and parallelism. Simulation results show that we can reduce the size of mapping set which poses difficulties on hardware-software partitioning by up to 80%.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.144-147
• /
• 2000

Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

• ETRI Journal
• /
• v.33 no.4
• /
• pp.611-620
• /
• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.1
• /
• pp.221-226
• /
• 2006

Around 2002, the United States Coast Guard (USCG) identified a need to re-capitalize their Reference Station (RS) and Integrity Monitor (IM) equipment used in the Nationwide Differential Global Position System (NDGPS). Commercially available off-the-shelf differential RS and IM equipment lacked the open architecture required to support long-term goals that include future system improvements such as use of new civil frequencies on L2 and L5 and realization of a higher rate NDGPS beacon data channel intended to support RTK. The first step in preparing for this future NDGPS was to port current RTCM SC-104 compatible RS and IM functionality onto an open architecture PC-based platform. Trimble's product Charisma is a PC-based RS and IM software designed to meet these USCG goals. In fact USCG engineers provided key designs and design insights throughout the development. We cannot overstate the contribution of the USCG engineers. Fundamental requirements for this effort were that it be sufficiently flexible in hardware and software design to support fluid growth and exploitation of new signals and technologies as they become available, yet remain backward compatible with legacy user receivers and existing site hardware and system architecture. These fundamental goals placed an implicit adaptability requirement on the design of the replacement RS and IM. Additionally, project engineers were to remain focused on sustaining the high level of differential GPS service that 1.5 million legacy users have come to depend on. This paper will present new hardware and software (i.e., Trimble's Charisma software) architecture for the next generation NDGPS RS and IM. This innovative approach to engineering on an open architecture PC-based platform allows the system to continue to fulfill legacy NDGPS system requirements and allows the USCG and others to pursue a scalable hardware re-capitalization strategy. We will use the USCG's recapitalization project to explain the essential role of the Charisma software.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.12S
• /
• pp.1210-1216
• /
• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability, and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean high speed train. The software controls the hardware of the measurement system and acts as interface between users and the system hardware. In this paper, practical experiment are performed to verify mechanical performance of motor and main transformer for Korean high speed rail. The experimental test carried out by using new temperature measurement method and verify the temperature performance of motor and transformer is verified.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.4
• /
• pp.779-787
• /
• 2010

In this paper, We introduce electrical tracking generated from surface activity associated with flow of leakage current on insulator under wet and contaminated conditions and design electrical tracking pattern recognition system by using LabVIEW. We measure the leaking current of contaminated wire by using LabVIEW software and the NI-c-DAQ 9172 and NI-9239 hardware. As pattern recognition algorithm and optimization algorithm for electrical tracking system, neural networks, Radial Basis Function Neural Networks(RBFNNs) and particle swarm optimization are exploited. The designed electrical tracking recognition system consists of two parts such as the hardware part of electrical tracking generator, the NI-c-DAQ 9172 and NI-9239 hardware and the software part of LabVIEW block diagram, LabVIEW front panel and pattern recognition-related application software. The electrical tracking system decides whether electrical tracking generate or not on electrical wire.

• Journal of the Korean Institute of Navigation
• /
• v.20 no.2
• /
• pp.77-84
• /
• 1996

This is the first report about the development of INMARSAT-C Satellite communication terminal. We analyze the existing Inmarsat-C terminal and examine each rules(IMO rule, domestic rules) about terminal. With that result, we design the basic hardware and software of terminal. This report consists of ; 1) the contents of the overall of operating situation and resources of INMARSAT-C system as like operation of communication system, communication channels and services 2) the contents of the specification of Inmarsat-C terminal hardware and software and the rules of IMO and Type approval 3) the design of basic hardware and reserch of signal modulation/demodulation using Viterbi algorithm 4) the design of software algorithms and functions focused in korean situations.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2001.10a
• /
• pp.354-358
• /
• 2001

Cosim (Hardware and Software Co-Simulator) is a JavaBeans-based simulation tool fur validating systems architecture and estimating performance of web applications. Cosim has four components: Modeler, Translator, Engine and Scenario. Users start from Modeler to describe systems architecture in UML(Unified Modeling Language) deployment diagram, and then specify hardware & software performance parameters such as execution delay, network topology, and frame size. All information specified on Modeler are sent to Translator, and then automatically converted to Java programs. Scenario is responsible to run the Java program and produce results in text reports and graphs. Developers can reduce development time and cost by validating systems architecture of web applications before the actual deployment.