• Journal of Broadcast Engineering
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• v.14 no.1
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• pp.70-80
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• 2009

We propose an ideal line coding for high speed data communication in visible light communication system. B4-HBT line coding is defined as follow. The 1 bit is +V at first though 1 encodes +Voltage and -Voltage doing change of shift each other, then -V newly. V that is been mutually contradictory for 1 bit that exist before that if continuous 0 bits exist 4 here same and reduces mistake because has reverse mark V in 4 continuous last 0 bits and gives half bit variation in 1 bit and made effect of noise low. 2${\sim}$3 dB profit is seen comparing with line coding that exist in simulation result.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.169-176
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• 2010

We propose a Z-HBT line coding for a LED-ID system. Z-HBT line coding is defined as follows. First, we apply half bit transition to one bit. Second, we decode encoded bits using difference of bit transition level in one bit duration. As a result, we obtain advantages about synchronization problem and noise effect mitigation at the receiver. We set up outdoor the LED-ID simulation environment. At simulation results, we show 2-3dB gain as compared with existing line coding schemes. The results of the paper can be applied to design and implementation of LED-ID systems for indoor wireless multimedia services.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.165-168
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• 2000

In this paper, the polyphase filter which has good ripple characteristic in the passband is proposed. This filter consists of the digital all-pass filter of parallel structure and it is the half-band filter with all zeros in unit circle. To approach easily in designing hardware, we determined the coefficients to the 16bit 1.15 format. To evaluate the performance of this filter, we analyzed the phase characteristic in each branch and simulated each filter with small coefficients. From the result, we have got to good ripple characteristic and also analyzed the fifth and the seventh, and compared them with four part : ripple, group delay, transition bandwidth, stopband attenuation.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.