• Proceedings of the KSME Conference
• /
• 2008.11a
• /
• pp.1053-1056
• /
• 2008

An application of CSG (Constructive Solid Geometry) modeling technique in Machining Simulation is introduced in this paper. The current CSG model is based on z-buffer CSG Rendering Algorithm. In order to build a CSG model, frame buffers of VGA (Video Graphic Accelerator) should be used in term of color buffer, depth buffer, and stencil buffer. In addition to using CSG model in machine simulation Stock and Cutter Swept Surface (CSS) should be solid. Method to create a solid Cuboid stock and Ball-end mill CSS are included in the present paper. Boolean operations are used to produce the after-cut part, especially the Difference operation between Stock and CSS as the cutter remove materials form stock. Finally, a small program called MaSim which simulates one simple cut using this method was created.

• Progress in Medical Physics
• /
• v.9 no.3
• /
• pp.127-136
• /
• 1998

On-line geometrical quality assurance system has been developed using electronic portal imaging system(OQuE). EPID system is networked into Pentium PC in order to transmit the acquisited images to analysis PC. Geometrical QA parameters, including light-radiation field congruence, collimator rotation axis, and gantry rotation axis can be easily analyzed with the help of graphic user interface(GUI) software. Equipped with the EPID (Portal Vision, Varian, USA), geometrical quality assurance of a linear accelerator (CL/2100/CD, Varian, USA), which is networked into OQuE, was performed to evaluate this system. Light-radiation field congruence tests by center of gravity analysis shows 0.2～0.3mm differences for various field sizes. Collimator (or Gantry) rotation axis for various angles could be obtained by superposing 4 shots of angles. The radius of collimator rotation axis is measured to 0.2mm for upper jaw collimator, and 0.1mm for lower jaw. Acquisited images for various gantry angles were rotated according to the gantry angle and actual center of image point obtained from collimator axis test. The rotated images are superpositioned and analyzed as the same method as collimator rotation axis. The radius of gantry rotation axis is calculated 0.3mm for anterior/posterior direction (gantry 0$^{\circ}$ and 170$^{\circ}$) and 0.7mm for right/left direction(gantry 90$^{\circ}$ and 260$^{\circ}$). Image acquisition for data analysis is faster than conventional method and the results turn out to be excellent for the development goal and accurate within a milimeter range. The OQuE system is proven to be a good tool for the geometrical quality assurance of linear accelerator using EPID.

• Journal of the Korean Society of Radiology
• /
• v.1 no.2
• /
• pp.23-30
• /
• 2007

This paper presents a method of generating 3-dimensional images by preprocessing 2-dimensional abdominal images obtained using CT (computed tomography) and MRI (magnetic resonance imaging) through segmentation, threshold technique, etc. and apply the method to virtual endoscopy. Three-dimensional images were visualized using indirect volume rendering, which can render at high speed using a general-purpose graphic accelerator used in personal computers. The algorithm used in the rendering is Marching Cubes, which has only a small volume of calculation. In addition, we suggested a method of producing 3-dimensional images in VRML (virtual reality modeling language) running on the Web browser without a workstation or an exclusive program. The number of nodes, the number of triangles and the size of a 3-dimensional image file from CT were 85,367, 174,150 and 10,124, respectively, and those from MRI were 34,029, 67,824 and 3,804, respectively.

• Journal of Internet Computing and Services
• /
• v.15 no.2
• /
• pp.41-47
• /
• 2014

In this paper, we implemented a CUDA Fortran parallel program to run the CFD_NIMR model on GP-GPU's, which simulates air diffusion on urban terrains. A GP-GPU is graphic processing unit in the form of a PCI card, and a general calculation accelerator to perform a large amount of high speed calculations with low cost and electric power. The GP-GPU gives performance enhancement of speed by 15 times to compare the Nvidia Tesla C1060 GPU with Intel XEON 2.0 GHz CPU. In addition, the program on a GP-GPU shows efficient performance compared to an MPI parallel program on multiple CPU's. It is expected that a proposed programming method on the GP-GPU parallel program can be used for numerical models with a similar structure.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.3
• /
• pp.563-569
• /
• 2007

As the mobile communication and the semiconductor technology is improved continuously, mobile contents such as the multimedia service and the 2D/3D graphics which require high level graphics are serviced recently. Mobile chips should consume small die area and low power. In this paper, we design a truncated floating-point multiplier that is useful for the 2D/3D vector graphics in mobile devices. The truncated multiplier is based on the radix-4 Booth's encoding algorithm and a truncation algorithm is used to achieve small area and low power. The average percent error of the multiplier is as small as 0.00003% and neglectable for mobile applications. The synthesis result using 0.35um CMOS cell library shows that the number of gates for the truncated multiplier is only 33.8 percent of the conventional radix-4 Booth's multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.101-109
• /
• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.