• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.156-156
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• 2000

Recently, the surface electronic states have attracted much attention since their standing wave patterns created around steps, defects, and adsorbates on noble metal surfaces such as Au(111), Ag(110), and Cu(111) were observed by scanning tunneling microscopy (STM). As a typical example, a striking circular pattern of "Quantum corral" observed by Crommie, Lutz, and Eigler, covers a number of text books of quantum mechanics, demonstrating a wavy nature of electrons. After the discoveries, similar standing waves patterns have been observed on other metal and demiconductor surfaces and even on a side polane of nano-tubes. With an expectation that the surface states could be utilized as one of ideal cases for studying two dimensionakl (sD) electronic system, various properties, such as mean free path / life time of the electronic states, have been characterized based on an analysis of standing wave patterns, . for the 2D electron system, electron density is one of the most importnat parameters which determines the properties on it. One advantage of conventional 2D electron system, such as the ones realized at AlGaAs/GaAs and SiO2/Si interfaces, is their controllability of the electrondensity. It can be changed and controlled by a factor of orders through an application of voltage on the gate electrode. On the other hand, changing the leectron density of the surface-state 2D electron system is not simple. On ewqy to change the electron density of the surface-state 2D electron system is not simple. One way to change the electron density is to deposit other elements on the system. it has been known that Pd(111) surface has unoccupied surface states whose energy level is just above Fermi level. Recently, we found that by depositing Pd on Cu(111) surface, occupied surface states of Cu(111) is lifted up, crossing at Fermi level around 2ML, and approaches to the intrinsic Pd surface states with a increase in thickness. Electron density occupied in the states is thus gradually reduced by Pd deposition. Park et al. also observed a change in Fermi wave number of the surface states of Cu(111) by deposition of Xe layer on it, which suggests another possible way of changing electron density. In this talk, after a brief review of recent progress in a study of standing weaves by STM, I will discuss about how the electron density can be changed and controlled and feasibility of using the surface states for a study of 2D electron system. One of the most important advantage of the surface-state 2D electron system is that one can directly and easily access to the system with a high spatial resolution by STM/AFM.y STM/AFM.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.