• Title/Summary/Keyword: gate bias

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Analysis of the Threshold Voltage Instability of Bottom-Gated ZnO TFTs with Low-Frequency Noise Measurements (Low-Frequency Noise 측정을 통한 Bottom-Gated ZnO TFT의 문턱전압 불안정성 연구)

  • Jeong, Kwang-Seok;Kim, Young-Su;Park, Jeong-Gyu;Yang, Seung-Dong;Kim, Yu-Mi;Yun, Ho-Jin;Han, In-Shik;Lee, Hi-Deok;Lee, Ga-Won
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.7
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    • pp.545-549
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    • 2010
  • Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

Design of Synchronous 256-bit OTP Memory (동기식 256-bit OTP 메모리 설계)

  • Li, Long-Zhen;Kim, Tae-Hoon;Shim, Oe-Yong;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1227-1234
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    • 2008
  • In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

Electrical response of tungsten diselenide to the adsorption of trinitrotoluene molecules (폭발물 감지 시스템 개발을 위한 TNT 분자 흡착에 대한 WSe2 소자의 전기적 반응 특성 평가)

  • Chan Hwi Kim;Suyeon Cho;Hyeongtae Kim;Won Joo Lee;Jun Hong Park
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.33 no.6
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    • pp.255-260
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    • 2023
  • As demanding the detection of explosive molecules, it is required to develop rapidly and precisely responsive sensors with ultra-high sensitivity. Since two-dimensional semiconductors have an atomically thin body nature where mobile carriers accumulate, the abrupt modulation carrier in the thin body channel can be expected. To investigate the effectiveness of WSe2 semiconductor materials as a detection material for TNT (Trinitrotoluene) explosives, WSe2 was synthesized using thermal chemical vapor deposition, and afterward, WSe2 FETs (Field Effect Transistors) were fabricated using standard photo-lithograph processes. Raman Spectrum and FT-IR (Fourier-transform infrared) spectroscopy reveal that the adsorption of TNT molecules induces the structural transition of WSe2 crystalline. The electrical properties before and after adsorption of TNT molecules on the WSe2 surface were compared; as -50 V was applied as the back gate bias, 0.02 μA was recorded in the bare state, and the drain current increased to 0.41 μA with a dropping 0.6% (w/v) TNT while maintaining the p-type behavior. Afterward, the electrical characteristics were additionally evaluated by comparing the carrier mobility, hysteresis, and on/off ratio. Consequently, the present report provides the milestone for developing ultra-sensitive sensors with rapid response and high precision.