• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.27-34
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• 1994

Block matching motion estimation is the most widely used method for motion compensated coding of image sequences. Based on a two dimensional systolic array, VLSI architecture and implementation of the full search block matching algorithm are described in this paper. The proposed architecture improves conventional array architecture by designing efficient processing elements that can control the data prodeuced by efficient search window division method. The advantages are that 1) it allows serial input to reduce pin counts for efficient composition of local memories but performs parallel processing. 2) It is flexible and can adjust to dimensional changes of search windows with simple control logic. 3) It has no idel time during the operation. 4) It can operate in real/time for low and main level in MPEG-2 standard. 5) It has modular and regular structure and thus is sutiable for VLSI implementation.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.3
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• pp.273-281
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• 2004

There is the temporal correlation of the video sequence between the motion vector of current block and the motion vector of previous block. In this paper, we propose the prediction search algorithm for block matching using the temporal correlation of the video sequence and the center-biased property of motion vectors. The proposed algorithm determines the location of a better starting point for the search of an exact motion vector using the point of the smallest SAD(sum of absolute difference) value by the predicted motion vector from the same block of the previous frame and the predictor candidate point on each search region. Simulation results show that PSNR(Peak-to-Signal Noise Ratio) values are improved up to the 1.06㏈ as depend on the video sequences and improved about 0.19∼0.46㏈ on an average except the full search(FS) algorithm.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.885-888
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• 2000

Among the previous searching methods, there are the typical methods such as full search and three-step search, etc. Block motion estimation using exhaustive search is too computationally intensive. To apply in practice, recently proposed fast algorithms have been focused on reducing the computational complexity by limiting the number of searching points. According to the reduction of searching points, the quality performance is aggravated in those algorithms. In this paper, We present a fast and efficient search algorithm for block motion estimation that produces better quality performance and less computational time compared with a three-step search (TSS). Previously the proposed Two Step Search Algorithm (TWSS) by Fang-Hsuan Cheng and San-Nan sun is based on the ideas of dithering pattern for pixel decimation using a part of a block pixels for BMA (Block Matching Algorithm) and multi-candidate to compensate quality performance with several locations. This method has good quality performance at slow moving images, but has bad quality performance at fast moving images. To resolve this problem, the proposed algorithm in this paper considers spatial and temporal correlation using neighbor and previous blocks to improve quality performance. This performance uses neighbor motion vectors and previous motion vectors in addition, thus it needs more searching points. To compensate this weakness, the proposed algorithm uses statistical character of dithering matrix. The proposed algorithm is superior to TWSS in quality performance and has similar computational complexity

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This paper presents a fast full search algorithm for motion estimation applicable to multiple reference images. The proposed method is an extended version of the rate constrained successive elimination algorithm (RSEA) for multiple reference frame applications. We will show that motion estimation for the reference images temporally preceding the first reference image can be less intensive in computation compared with that for the first reference image. for computational reduction, we will drive a new condition to lead the smaller number of candidate blocks for the best matched block. Simulation results explain that our method reduces computation complexity although it has the same quality as RSEA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.594-600
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• 2017

This paper proposes a global search based motion estimation algorithm for high performance HEVC encoder and its hardware architecture. To eliminate temporal redundancy, motion estimation in HEVC inter-view prediction uses global search and fast search algorithm to search for a predicted block having a high correlation with the current PU in an interpolated reference picture. The global search method predicts the motion of all candidate blocks in a given search area, thus ensuring optimal results, but has a disadvantage of large computation time. Therefore we propose a new algorithm that reduces computational complexity by reusing SAD operation in global search to reduce computation time of inter prediction. As a result of applying the proposed algorithm to standard software HM16.12, the computation time was reduced by 61%, BDBitrate by 11.81%, and BDPSNR by about 0.5% compared with the existing search algorithm. As a result of hardware design, the maximum operating frequency is 255 MHz and the total number of gates is 65.1K.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1401-1410
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• 1999

In this paper, we propose a fast block matching algorithm using the lower and upper bound of mean absolute difference (MAD) which is calculated at the search region overlapped with neighbor blocks. At first, we calculate the lower bound of MAD and reduce the search point by using this lower bound. In this method, we can get good prediction error performance close to full search block matching algorithm (FSBMA), but there exists some computational complexity that has to be reduced. Therefore, we further reduce the computational complexity by using pixel subsampling besides the lower and upper bound of MAD. Experimental results show that we can remarkably reduce the computational complexity with good prediction error performance close to FSBMA.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.521-523
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• 2006

This paper proposes an algorithm and its data structure to support real-time full-text search for the streamed or broadcasted multimedia data containing real-time stenograph text. Since the traditional indexing method used at information retrieval area uses the linguistic information, there is a heavy cost. Therefore, we propose the algorithm and its data structure based on suffix array, which is a simple data structure and has low space complexity. Suffix array is useful frequently to search for huge text. However, subtitle text of multimedia data is to get longer by time. Therefore, suffix array must be reconstructed because subtitle text is continually changed. We propose the data structure called prefix array and search algorithm using it.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.6
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• pp.35-48
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• 1993

In this paper, a hierarchical motion vector estimation algorithm using pyramidal structure is proposed. Using a smaller measurement window at each level of a pyramid than that of the conventional scheme, the proposed algorithm, based on the TSS(three step search), reduces the computational complexity greatly with its performance comparable to that of the TSS. By increasing the number of cnadidate motion vectors which are to be used as the initial search points for motion vector estimation at the next level, the performance improves further. Then the computational complexity of the proposed hierarchical algorithm depends on the number of candidate motion vectors, with its PSNR (peak signal to noise ratio) ranging between those of the TSS and the full search method. The simulation results with two different block sizes and various test sequences are given and its hardware implementation is also sketched.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.54-63
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• 2000

We present a multi-resolution block matching algorithm (BMA) for fast motion estimation At the coarsest level, a motion vector (MV) having minimum matching error is chosen via a full search, and a MV with minimum matching error is concurrently found among the MVs of the spatially adjacent blocks Here, to examine the spatial MVs accurately, we propose an efficient method for searching full resolution MV s without MV quantization even at the coarsest level The chosen two MV s are used as the initial search centers at the middle level At the middle level, the local search is performed within much smaller search area around each search center If the method used at the coarsest level is adopted here, the local searches can be done at integer-pel accuracy A MV having minimum matching error is selected within the local search areas, and then the final level search is performed around this initial search center Since the local searches are performed at integer-pel accuracy at the middle level, the local search at the finest level does not take an effect on the overall performance So we can skip the final level search without performance degradation, thereby the search speed increases Simulation results show that in comparison with full search BMA, the proposed BMA without the final level search achieves a speed-up factor over 200 with minor PSNR degradation of 02dB at most, under a normal MPEG2 coding environment Furthermore, our scheme IS also suitable for hardware implementation due to regular data-flow.