• Current Optics and Photonics
• /
• v.6 no.6
• /
• pp.634-641
• /
• 2022

A frequency stable and tunable optoelectronic oscillator (OEO) incorporating an optical phase shifter and a phase-shifted fiber Bragg grating (PS-FBG) is designed and analyzed. The frequency tunability of the OEO can be realized by using a tunable microwave photonic bandpass filter consisting of a PS-FBG, a phase modulator. The optical phase compensation loop is used to compensate for the phase variations of the RF signal from the OEO by adjusting an optical phase shifter. Simulation results demonstrate that the output RF signals of the OEO can be tuned in a frequency range of 118 MHz to 24.092 GHz. When the ambient temperature fluctuates within ±3.9 ℃, the frequency drifts of the output RF signals are less than 68 Hz, the side-mode suppression ratios are more than 69.39 dB, and the phase noise is less than -92.49 dBc/Hz at a 10 kHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.2
• /
• pp.66-72
• /
• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.5
• /
• pp.118-125
• /
• 2008

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.7
• /
• pp.1229-1236
• /
• 2016

In underwater acoustic multipath channel, a performance of underwater acoustic (UWA) communication systems is affected by dynamic variation of boundary and high temporal and spatial variability of the channel conditions. Time and spatial variations of UWA channel induce a carrier frequency offset (CFO) since a phase and a frequency of received signal mismatch with a transmitting signal. Therefore, a performance of a phase shift keying underwater acoustic communication system is degraded. In this study, we have analyzed a performance of CFO estimation and compensation using a phase code in time and spatial variation channel. A constant amplitude zero autocorrelation (CAZAC) signal is applied as a phase code signal and its performance is evaluated in water tank. The bit error rate of a quadrature phase shift keying (QPSK) system with a phase code is improved about 4 to 10 times better than that without a phase code.

• The KIPS Transactions:PartC
• /
• v.16C no.2
• /
• pp.229-236
• /
• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area networks. The clock frequency differences of nodes have serious affects on asynchronous ranging methods to estimate locations of mobile nodes. The specification of high rate UWB describes successive TWR method with the estimation of a relative clock frequency offset. In this paper, we complete the ranging equations using relative frequency offset and time information, and propose a method to estimate the exact frequency offsets. We evaluate the ranging algorithms with simulation. The results show that the performances of the algorithms using frequency offsets are very close without noise. But, at noise environment, the method of exact frequency offsets shows better performance than that of relative frequency offsets.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2004.11a
• /
• pp.366-366
• /
• 2004

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.4A
• /
• pp.247-255
• /
• 2003

In this paper, an $tan^{-1}$ circuit for the frequency synchronization of OFDM based IEEE 802.11a is presented. The proposed circuit consists of a divider, an $tan^{-1}$ ROM and a phase detector, which can detect frequency offset within 0.0491 rad. The circuit implemented with FPGA shows a pull-in range of under ${\pm}625KHz$ at 5dB AWGN. It may be useful for IEEE 802.11a WLAN standard.

• Journal of Broadcast Engineering
• /
• v.15 no.2
• /
• pp.217-223
• /
• 2010

In this paper, an interchannel interference (ICI) cancellation method is proposed for multiple frequency offsets in orthogonal frequency division multiplexing (OFDM) systems. When several same signals are received from different transmitters simultaneously, multiple frequency offsets may occur at the receiver because of the frequency difference of the oscillators of the two transmitters and the receiver. This causes degradation of system performance because OFDM systems are very sensitive to the frequency offsets. In this paper, we propose a method to eliminate the effect of the multiple frequency offsets for OFDM systems. The method is accomplished in two steps: compensation of the frequency offset in the time domain and subsequent cancellation of the ICI in the frequency domain. Through computer simulations, we verify the effectiveness of the proposed ICI cancellation method.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.3
• /
• pp.455-464
• /
• 2019

The sensorless control based on the flux linkage of PM synchronous motors has excellent position estimation characteristics at low speeds. However, a limitation arises because the integrator of flux estimator is saturated by the DC offset generated during the analog to digital conversion(ADC) process of the measured current. In order to overcome this limitation, HPF with a low cutoff frequency is used. However, the estimation performance is deteriorated (Ed- the verb deteriorate already includes the meaning of 'problem') at high speed due to the low cutoff frequency, and increasing the cutoff frequency of the HPF induces further problems of phase leading and initial starting failure at low speeds. In this paper, the cutoff frequency of HPF was synchronized to the operation frequency of the motor: at low speeds the cutoff frequency was set to low in order to reduce the phase leading of the estimated flux, and at high speeds it was set to high to raise the DC offset removal performance. As a result, the operating range was increased by 200%. Furthermore, a phase compensation algorithm is proposed to reduce the phase leading of the HPF to less than 1.5 degrees over the full operating range. The proposed sensorless control algorithm was verified by experiment with a PM synchronous motor for a washing machine.

• Proceedings of the KIPE Conference
• /
• 2004.11a
• /
• pp.32-36
• /
• 2004

In order to achieve high performance vector control, it is essential to measure accurate ac current. The errors generated from current path are inevitable, and they could be divided into two categories: offset error and scaling error. The current data including these errors cause periodic speed ripples which are one and two times of stator electrical frequency respectively. Since these undesirable ripples bring about bad influences to motor driving system, a compensation algorithm must be needed in the control algorithm of the motor drive. In this paper, a new compensation algorithm is proposed. The signal of the integrator output of the d-axis current regulator is chosen and processed to compensate the current measurement errors. The compensation of the current measurement errors is easily implemented to smooth the signal of the integrator output of the d-axis current regulator by subtracting the DC offset value or rescaling the gain of the hall sensor. Therefore, the proposed algorithm has several features: the robustness of the variation of the mechanical parameters, the application of the steady and transient state, the easy implementation, and less computation time.