• Journal of IKEEE
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• v.25 no.1
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• pp.174-179
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• 2021

An Edwards curve cryptography (EdCC) core supporting point scalar multiplication (PSM) on Edwards curves of Edwards25519 and Edwards448 was designed. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted to implement point operations without division operation. As a result of synthesizing the EdCC core with 100 MHz clock, it was implemented with 24,073 equivalent gates and 11 kbits RAM, and the maximum operating frequency was estimated to be 285 MHz. The evaluation results show that the EdCC core can compute 299 and 66 PSMs per second on Edwards25519 and Edwards448 curves, respectively. Compared to the ECC core with similar structure, the number of clock cycles required for 256-bit PSM was reduced by about 60%, resulting in 7.3 times improvement in computational performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.695-698
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• 2005

The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• Journal of Plant Biology
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• v.33 no.4
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• pp.271-276
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• 1990

Our study was carried out for plant regeneration via somatic embryogenesis from immature seeds of Bletilla striata. The highest frequency of embryogenic callus formation was obtained from the immature seeds (at 150 days after pollination) cultured on Hyponex and VW medium supplemented with 3 mg/l 2,4-dichlorophenoxyacetic acid (2,4-D) and 1 mg/l kinetin under the dark condition. Multiple somatic embryos were induced when embryogenic callus was transferred to VW medium without growth regulators under continued illumination. Somatic embryos were observed histologically with scanning electron microscopy. Regeneration of Bletilla striata was obtained from somatic embryos with a well-defined scutellum and coleoptile as well as with one or more shoot primordia and root primordia. We think that these methods for orchid multiplication must be useful to access clonal propagation of orchids.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.6
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• pp.327-334
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• 1985

A new method on the hardware implementation of multi-channel Finite Impulse Response(FIR) digital filter using vector multiplication structure is proposed. The proposed method can reduce the complexity of hardware structure and improve execution speed. The frequency response of four channel digital filter implemented by the above method is quite agreeable with the frquency response simulated by Remez method.

• Journal of the Optical Society of Korea
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• v.8 no.1
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• pp.29-33
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• 2004

We propose and demonstrate a novel optical pulse multiplier applicable to OTDM (Optical Time Division Multiplexing) systems using cascaded long-period fiber gratings. We have exploited the fact that each mode in a fiber has a different propagation constant to obtain time delays among optical pulses. The proposed scheme could realize high-frequency optical pulse multiplication for optical short pulse trains. We have successfully implemented two, four, and eight times multiplications with the maximum repetition rate of 416.7 ㎓. The obtained pulse delays are well matched with the simulated ones.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.1
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• pp.22-26
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• 1967

The efficiency of frequency multiplier using nonlinear elements varies with the characteristics of the elements and also varies with the order of multiplication. And, if the elements is resistive, the efficiency varies with reverse-to-forward resistance value. Microwave energy which was frequency doubled by a nonlinear resistive element was obtained, and the theoretical efficiency of nonlinear reactive and resistive multiplier were compared with the efficiency taken by experiments. It was found that efficiency of frequency multiplier using the nonlinear resistive elements was increased, without depending on frequency, with the reverse-to-forward resistance value.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1386-1392
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• 2009

An analysis is presented for super-high-speed optical demodulation by an avalanche photodiode(APD) with electric mixing. A normalized gain is defined to evaluate the performance of the optical mixing detection. Unlike previous work, we include the effect of the nonlinear variation of the APD capacitance with bias voltage as well as the effect of parasitic and amplifier input capacitance. As a results, the normalized gain is dependent on the signal frequency and the frequency difference between the signal and the local oscillator frequency. However, the current through the equivalent resistance of the APD is almost independent of signal frequency. The mixing output is mainly attributed to the nonlinearity of the multiplication factor. We show also that there is an optimal local oscillator voltage at which the normalized gain is maximized for a given avalanche photodiode.