• KSCE Journal of Civil and Environmental Engineering Research
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• v.26 no.3D
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• pp.367-374
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• 2006

This research revealed the operation problems of the current crossing control systems through inspecting and testing the obstacle detection systems and gate control systems for the crossings. To resolve the problems of the crossing control systems, this research developed new algorithms of four-quadrant gate system and obstacle detection systems combing the functions of rasar sensors and magnetic sensors and tested the reliability of the systems. Currently, the obstacle detection systems and gate control systems controls approaching and departing traffic by simply detecting vehicles and obstacles but do not consider traffic movements at the crossings. In addition, they do not make signal cooperation for gate controls. As a result, such inefficient crossing controls result in unsafe gate controls for drivers. Therefore, the newly developed crossing control systems through this study will provide more effective crossing control services with more strengthen information cooperation within control systems. Besides they will help to reduce train crashes at the crossings by gate control systems considering various driving behaviors.

• Proceedings of the KOR-KST Conference
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• 1999.10a
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• pp.155-160
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• 1999

이 연구는 도로상의 신호사거리에서 신호변환시 발생하는 혼돈지역의 개념을 이용하여 도로-철도 교차로에 설치되는 사각차단기의 운영시간을 결정하는 방법론을 제시한다. 이 방법론은 현재 미국 일리노이주에서 시카고-세인트루이스의 고속전철 노선중 6개의 교차로에 설치중인 사각차단기의 운영시간을 설정하여 제시함으로써 현장검증이 되었다. 특히, 운전자가 교차로 진입시 차단기 사이에 차량이 걸리지 않으며 혹은 정지시 안전하게 교차로 앞에서 정지하도록 하는 의사결정이 이루어 지도록 최적의 차단기 운영시간을 운전자에게 제시하였다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.301-304
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• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.500-504
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• 1997

Current source inverter drives of auto sequentially commutated type are very popular in high power applications, because of simple power circuit configuration with four quadrant operation. But the six-step current output create harmonic problems and the input power factor of such a drive is not always good. In this respect pulse width modulated drives using gate turn off thyristors ( GTO ) are finding application, especially in traction drives. However the switching and snubber loses of a GTO do not permit the inverter switching frequency go beyond a few hundred hertz.This will again introduce low frequency harmonic problems. Multi level inverters of the 3-level and 5-level can be considered as an alternative to overcome the low switching frequency harmonic problem of the 2-level GTO inverters. But with multi level inverters the complexity of the power circuit increases. In this paper a combination of multi level ( 2-level and 3-level ) inverters and multi phase induction motor ( 3-phase and 6-phase) configurations are presented for high power VSI drives for traction applications with reduced inverter switching frequency requirements coupled with reduced voltage rating for the power switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.