• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.415-422
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• 2010

This paper proposes service-oriented composition and verification techniques for incrementally extracting high-level abstract behavior of unit components in a systematic manner. Proposed techniques include the definition for abstract component, which is a basic building-block of the abstraction process, an algorithm for port-based synchronized abstraction, and projection abstraction. A verification framework is developed using the proposed techniques and its efficiency is demonstrated through a case example.

• The KIPS Transactions:PartD
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• v.11D no.4
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• pp.855-864
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• 2004

Programmers can be got the test-related information for implementation without interference of source code complexity by use of the formal specification. Especially the external inputs and system responses can be represented precisely by formal specification in testing phase of web-based software systems. This paper suggests a method of extracting test cases by use of formal specification. Object-Z formal specification represents various test-related information for complex functions of web-based applications. State Transition Models could be built from the formal specification so that test scenarios were extracted from STDs from the highest level to detail levels. The target system for verification of this method is a web-based banking system which is necessary to be secured and critical on errors. This method would be an important factor in automatizing test procedure for web-based application software systems combining the user-base test technique.

• Journal of KIISE:Software and Applications
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• v.27 no.1
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• pp.1-12
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• 2000

Model checking is a formal verification technique which checks the consistency between a requirement specification and a behavior model of the system by explorating the state space of the model. We apply model checking to the formal verification of the concurrent object-oriented system, using an existing model checker SPIN which has been successful in verifying concurrent systems. First, we propose an Actor-based modeling language, called APromela, by extending the modeling language Promela which is a modeling language supported in SPIN. APromela supports not only all the primitives of Promela, but additional primitives needed to model concurrent object-oriented systems, such as class definition, object instantiation, message send, and synchronization.Second, we provide translation rules for mapping APromela's such modeling primitives to Promela's. As an application of APromela, we suggest a verification method for UML models. By giving an example of specification, translation, and verification, we also demonstrate the applicability of our proposed approach, and discuss the limitations and further research issues.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.40-42
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• 2002

캐쉬 일관성 유지 프로토콜은 공유 메모리 다중 프로세서 시스템의 정확하고 효율적인 작동에 중요하다. 시스템이 점점 복잡해짐에 따라 시뮬레이션 방법만으로는 프로토콜의 정확성을 확인하기는 어렵다. 본 논문에서는 CC-NUMA용 디렉토리 기반 캐쉬 일관성 프로토콜인 RACE 프로토콜을 정형기법 도구인 ESTEREL을 이용하여 프로토콜이 안정적으로 동작함을 검증하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.68-69
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• 2008

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.769-771
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• 2001

인터넷의 급속한 발달과 이를 통한 다양한 서비스가 확산됨에 따라, 인증과 보안은 아주 중요한 분야로 대두되고 있다. 본 논문에서는 Egterl 을 이용하여 최근 정보화 사회에서 개인적 정보 뿐만 아니라 비즈니스 간의 데이터 응용 분야에 이르기까지 폭 넓게 사용되어지고 있는 스마트 카드의 인증과 보안 시스템 대한 모델링 및 정형검증에 대해 논한다.

• The KIPS Transactions:PartD
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• v.16D no.3
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• pp.339-352
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• 2009

There are a number of formal methods for distributed real-time systems in ubiquitous computing to analyze and verify the behavioral, temporal and the spatial properties of the systems. However most of the methods reveal structural and fundamental limitations of complexity due to mixture of spatial and behavioral representations. Further temporal specification makes the complexity more complicate. In order to overcome the limitations, this paper presents a new formal method, called Timed Calculus of Abstract Real-Time Distribution, Mobility and Interaction(t-CARDMI). t-CARDMI separates spatial representation from behavioral representation to simplify the complexity. Further temporal specification is permitted only in the behavioral representation to make the complexity less complicate. The distinctive features of the temporal properties in t-CARDMI include waiting time, execution time, deadline, timeout action, periodic action, etc. both in movement and interaction behaviors. For analysis and verification of spatial and temporal properties of the systems in specification, t-CARDMI presents Timed Action Graph (TAG), where the spatial and temporal properties are visually represented in a two-dimensional diagram with the pictorial distribution of movements and interactions. t-CARDMI can be considered to be one of the most innovative formal methods in distributed real-time systems in ubiquitous computing to specify, analyze and verify the spatial, behavioral and the temporal properties of the systems very efficiently and effectively. The paper presents the formal syntax and semantics of t-CARDMI with a tool, called SAVE, for a ubiquitous healthcare application.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.513-519
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• 2006

As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.354-357
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• 2004

According to the computerization of railway signaling systems, the interface link between the signaling systems has been replaced by the digital communication channel. At the same time, the importance of the communication link is more pronounced than in the past. In this paper, new network-based protocol for Korean railway signaling has designed between CTC and SCADA system, and the overview of designed protocol is briefly represented. Using the informal method for specifying the communication protocol, a little ambiguity may be contained in the protocol. To clear the ambiguity contained in the designed protocol, we use LTS model to design the protocol for this interface link between CTC and SCADA, the LTS is an intermediate model for encoding the operational behavior of processes. And then, we verify automatically and formally the safety and the liveness properties through the model checking method. Especially, the modal ${\mu}$-calculus, which is a highly expressive method of temporal logic that has been applied to the model checking method. It will be expected to increase the safety, reliability and efficiency of maintenance of the signaling systems by using the designed protocol for railway signaling in Korea.